+def regspec_decode(e, regfile, name):
+ """regspec_decode
+
+ this function encodes the understanding (relationship) between
+ Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2).
+
+ based on the regspec, which contains the register file name and register
+ name, return a tuple of:
+
+ * how the decoder should determine whether the Function Unit needs
+ a Regport or not
+ * which Regfile port should be read to get that data
+ * when it comes to writing: likewise, which Regfile port should be written
+
+ Note that some of the port numbering encoding is *unary*. in the case
+ of "Full Condition Register", it's a full 8-bit mask of read/write-enables.
+ This actually matches directly with the XFX field in MTCR, and at
+ some point that 8-bit mask from the instruction could actually be passed directly through to full_cr (TODO).
+
+ For the INT and CR numbering, these are expressed in binary in the
+ instruction (note however that XFX in MTCR is unary-masked!)
+
+ XER is implicitly-encoded based on whether the operation has carry or
+ overflow.
+
+ FAST regfile is, again, implicitly encoded, back in PowerDecode2, based
+ on the type of operation (see DecodeB for an example).
+
+ The SPR regfile on the other hand is *binary*-encoded, and, furthermore,
+ has to be "remapped".
+ """
+