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mmu.py comments
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 21 Dec 2021 04:53:45 +0000
(
04:53
+0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 21 Dec 2021 04:53:45 +0000
(
04:53
+0000)
src/soc/experiment/mmu.py
patch
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diff --git
a/src/soc/experiment/mmu.py
b/src/soc/experiment/mmu.py
index c70ba8c4722ef545a5a8596d3441a33fedaf3f66..376f84051b9d6e064276c124d49a27078f81429c 100644
(file)
--- a/
src/soc/experiment/mmu.py
+++ b/
src/soc/experiment/mmu.py
@@
-326,13
+326,14
@@
class MMU(Elaboratable):
with m.If(leaf):
# check permissions and RC bits
with m.If(r.priv | ~eaa[EAA_PRIV]):
with m.If(leaf):
# check permissions and RC bits
with m.If(r.priv | ~eaa[EAA_PRIV]):
- with m.If(~r.iside):
- comb += perm_ok.eq(eaa[EAA_WR] |
- (eaa[EAA_RD] & ~r.store))
- with m.Else():
+ with m.If(r.iside): # instruction-side request
# no IAMR, so no KUEP support for now
# deny execute permission if cache inhibited
comb += perm_ok.eq(eaa[EAA_EXE] & ~rpte.att[1])
# no IAMR, so no KUEP support for now
# deny execute permission if cache inhibited
comb += perm_ok.eq(eaa[EAA_EXE] & ~rpte.att[1])
+ with m.Else():
+ # Load/Store (read/write)
+ comb += perm_ok.eq(eaa[EAA_WR] |
+ (eaa[EAA_RD] & ~r.store))
comb += rc_ok.eq(rpte.r & (rpte.c | ~r.store))
# permissions / rc ok, load TLB, otherwise report error
comb += rc_ok.eq(rpte.r & (rpte.c | ~r.store))
# permissions / rc ok, load TLB, otherwise report error