move PriorityCombMuxInPipe to multipipe

diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index b174cf6b0572d9039cae3e6138d7aaf53afd5e5c..2f54c471d0adae7bdd1e891faeefd43d430457ef 100644 (file)
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -302,18 +302,18 @@ class InputPriorityArbiter:
 
 
 
 
 
 

-class ExamplePipeline(CombMultiInPipeline):
+class PriorityCombMuxInPipe(CombMultiInPipeline):

     """ an example of how to use the combinatorial pipeline.
     """
 
     """ an example of how to use the combinatorial pipeline.
     """
 

-    def __init__(self, p_len=2):
+    def __init__(self, stage, p_len=2):

         p_mux = InputPriorityArbiter(self, p_len)
         p_mux = InputPriorityArbiter(self, p_len)

-        CombMultiInPipeline.__init__(self, ExampleStage, p_len, p_mux)
+        CombMultiInPipeline.__init__(self, stage, p_len, p_mux)

 
 
 if __name__ == '__main__':
 
 
 
 if __name__ == '__main__':
 

-    dut = ExamplePipeline()
+    dut = PriorityCombMuxInPipe(ExampleStage)

     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_combpipe.il", "w") as f:
         f.write(vl)
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_combpipe.il", "w") as f:
         f.write(vl)

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 3fa5b4452050276da3a30bcc6cf505fc53b6cf6f..865783a9c7f91e695a5fdd8a07b2557023cb6607 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -11,7 +11,7 @@ from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
 from fpbase import MultiShiftRMerge, Trigger
 from singlepipe import (ControlBase, StageChain, UnbufferedPipeline)
 from multipipe import CombMultiOutPipeline
 from fpbase import MultiShiftRMerge, Trigger
 from singlepipe import (ControlBase, StageChain, UnbufferedPipeline)
 from multipipe import CombMultiOutPipeline

-from multipipe import CombMultiInPipeline, InputPriorityArbiter
+from multipipe import PriorityCombMuxInPipe

 
 #from fpbase import FPNumShiftMultiRight
 
 
 #from fpbase import FPNumShiftMultiRight
 


@@ -1910,15 +1910,6 @@ class FPADDBasePipe(ControlBase):
         return m
 
 
         return m
 
 

-class PriorityCombPipeline(CombMultiInPipeline):
-    def __init__(self, stage, p_len):
-        p_mux = InputPriorityArbiter(self, p_len)
-        CombMultiInPipeline.__init__(self, stage, p_len=p_len, p_mux=p_mux)
-
-    def ports(self):
-        return self.p_mux.ports()
-
-

 class FPAddInPassThruStage:
     def __init__(self, width, id_wid):
         self.width, self.id_wid = width, id_wid
 class FPAddInPassThruStage:
     def __init__(self, width, id_wid):
         self.width, self.id_wid = width, id_wid


@@ -1927,13 +1918,11 @@ class FPAddInPassThruStage:
     def process(self, i): return i
 
 
     def process(self, i): return i
 
 

-class FPADDInMuxPipe(PriorityCombPipeline):
+class FPADDInMuxPipe(PriorityCombMuxInPipe):

     def __init__(self, width, id_width, num_rows):
         self.num_rows = num_rows
         stage = FPAddInPassThruStage(width, id_width)
     def __init__(self, width, id_width, num_rows):
         self.num_rows = num_rows
         stage = FPAddInPassThruStage(width, id_width)

-        PriorityCombPipeline.__init__(self, stage, p_len=self.num_rows)
-        #self.p.i_data = stage.ispec()
-        #self.n.o_data = stage.ospec()
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)

 
     def ports(self):
         res = []
 
     def ports(self):
         res = []

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index 36c4d991ffd51c63595da6b60765f062ad6a7e42..c30ba644664471000b6783a3bb313ed5dc6520f4 100644 (file)
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -1,4 +1,4 @@
-""" key strategic example showing how to do multi-input fan-in into a 
+""" key strategic example showing how to do multi-input fan-in into a

     multi-stage pipeline, then multi-output fanout.
 
     the multiplex ID from the fan-in is passed in to the pipeline, preserved,
     multi-stage pipeline, then multi-output fanout.
 
     the multiplex ID from the fan-in is passed in to the pipeline, preserved,


@@ -12,20 +12,10 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMultiOutPipeline
 from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMultiOutPipeline

-from multipipe import CombMultiInPipeline, InputPriorityArbiter
+from multipipe import PriorityCombMuxInPipe

 from singlepipe import UnbufferedPipeline
 
 
 from singlepipe import UnbufferedPipeline
 
 

-class PriorityCombPipeline(CombMultiInPipeline):
-    def __init__(self, stage, p_len):
-        p_mux = InputPriorityArbiter(self, p_len)
-        CombMultiInPipeline.__init__(self, stage, p_len=p_len, p_mux=p_mux)
-
-    def ports(self):
-        return self.p_mux.ports()
-        #return UnbufferedPipeline.ports(self) + self.p_mux.ports()
-
-

 class MuxCombPipeline(CombMultiOutPipeline):
     def __init__(self, stage, n_len):
         # HACK: stage is also the n-way multiplexer
 class MuxCombPipeline(CombMultiOutPipeline):
     def __init__(self, stage, n_len):
         # HACK: stage is also the n-way multiplexer


@@ -66,7 +56,7 @@ class PassThroughStage:
         return PassData()
     def ospec(self):
         return self.ispec() # same as ospec
         return PassData()
     def ospec(self):
         return self.ispec() # same as ospec

-                
+

     def process(self, i):
         return i # pass-through
 
     def process(self, i):
         return i # pass-through
 


@@ -160,11 +150,11 @@ class InputTest:
         print ("recv ended", mid)
 
 
         print ("recv ended", mid)
 
 

-class TestPriorityMuxPipe(PriorityCombPipeline):
+class TestPriorityMuxPipe(PriorityCombMuxInPipe):

     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()

-        PriorityCombPipeline.__init__(self, stage, p_len=self.num_rows)
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)

 
     def ports(self):
         res = []
 
     def ports(self):
         res = []