When some operands are not used (zero_a and/or imm_ok), raise an error as
soon as rel_o is asserted. Likewise, for results (when not in RA update
mode).
# transaction parameters, passed via signals
self.delay = Signal(8)
self.data = Signal.like(self.port)
# transaction parameters, passed via signals
self.delay = Signal(8)
self.data = Signal.like(self.port)
+ self.data_valid = False
# add ourselves to the simulation process list
sim.add_sync_process(self._process)
# add ourselves to the simulation process list
sim.add_sync_process(self._process)
yield
yield Settle()
# read the transaction parameters
yield
yield Settle()
# read the transaction parameters
+ assert self.data_valid, "an unexpected operand was consumed"
delay = (yield self.delay)
data = (yield self.data)
# wait for `delay` cycles
delay = (yield self.delay)
data = (yield self.data)
# wait for `delay` cycles
yield self.port.eq(data)
yield self.count.eq(self.count + 1)
yield
yield self.port.eq(data)
yield self.count.eq(self.count + 1)
yield
+ self.data_valid = False
yield self.go_i.eq(0)
yield self.port.eq(0)
yield self.go_i.eq(0)
yield self.port.eq(0)
"""
yield self.data.eq(data)
yield self.delay.eq(delay)
"""
yield self.data.eq(data)
yield self.delay.eq(delay)
# transaction parameters, passed via signals
self.delay = Signal(8)
self.expected = Signal.like(self.port)
# transaction parameters, passed via signals
self.delay = Signal(8)
self.expected = Signal.like(self.port)
# add ourselves to the simulation process list
sim.add_sync_process(self._process)
# add ourselves to the simulation process list
sim.add_sync_process(self._process)
yield
yield Settle()
# read the transaction parameters
yield
yield Settle()
# read the transaction parameters
+ assert self.expecting, "an unexpected result was produced"
delay = (yield self.delay)
expected = (yield self.expected)
# wait for `delay` cycles
delay = (yield self.delay)
expected = (yield self.expected)
# wait for `delay` cycles
"""
yield self.expected.eq(expected)
yield self.delay.eq(delay)
"""
yield self.expected.eq(expected)
yield self.delay.eq(delay)
def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):