projects
/
soc.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
d3a46d6
)
Consolidate every pipe_data to use alu's integer data
author
Michael Nolan
<mtnolan2640@gmail.com>
Sat, 16 May 2020 15:19:21 +0000
(11:19 -0400)
committer
Michael Nolan
<mtnolan2640@gmail.com>
Sat, 16 May 2020 15:19:21 +0000
(11:19 -0400)
src/soc/alu/pipe_data.py
patch
|
blob
|
history
src/soc/branch/pipe_data.py
patch
|
blob
|
history
src/soc/cr/pipe_data.py
patch
|
blob
|
history
src/soc/logical/pipe_data.py
patch
|
blob
|
history
src/soc/shift_rot/pipe_data.py
patch
|
blob
|
history
diff --git
a/src/soc/alu/pipe_data.py
b/src/soc/alu/pipe_data.py
index 13be974706a423cec4f085f290e1302427533584..c386397aa2f26b0b62550c260ef56aff529c24de 100644
(file)
--- a/
src/soc/alu/pipe_data.py
+++ b/
src/soc/alu/pipe_data.py
@@
-16,6
+16,9
@@
class IntegerData:
def eq(self, i):
return [self.ctx.eq(i.ctx)]
def eq(self, i):
return [self.ctx.eq(i.ctx)]
+ def ports(self):
+ return self.ctx.ports()
+
class ALUInputData(IntegerData):
def __init__(self, pspec):
class ALUInputData(IntegerData):
def __init__(self, pspec):
diff --git
a/src/soc/branch/pipe_data.py
b/src/soc/branch/pipe_data.py
index 3d3b9afbf026ea6b2ef40b1353082ad4a17f9352..351ca5ec63f1e31433eb842863bbf3606a9663ff 100644
(file)
--- a/
src/soc/branch/pipe_data.py
+++ b/
src/soc/branch/pipe_data.py
@@
-32,20
+32,9
@@
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from soc.decoder.power_decoder2 import Data
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from soc.decoder.power_decoder2 import Data
+from soc.alu.pipe_data import IntegerData
-class IntegerData:
-
- def __init__(self, pspec):
- self.ctx = FPPipeContext(pspec)
- self.muxid = self.ctx.muxid
-
- def __iter__(self):
- yield from self.ctx
-
- def eq(self, i):
- return [self.ctx.eq(i.ctx)]
-
class BranchInputData(IntegerData):
def __init__(self, pspec):
super().__init__(pspec)
class BranchInputData(IntegerData):
def __init__(self, pspec):
super().__init__(pspec)
diff --git
a/src/soc/cr/pipe_data.py
b/src/soc/cr/pipe_data.py
index bb248c23ba9a538f9554ea9b87e171231ffdeb7a..d56c8f3fac22fe48aee73aa34666afed7f1e292a 100644
(file)
--- a/
src/soc/cr/pipe_data.py
+++ b/
src/soc/cr/pipe_data.py
@@
-1,18
+1,6
@@
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
-
-
-class IntegerData:
-
- def __init__(self, pspec):
- self.ctx = FPPipeContext(pspec)
- self.muxid = self.ctx.muxid
-
- def __iter__(self):
- yield from self.ctx
-
- def eq(self, i):
- return [self.ctx.eq(i.ctx)]
+from soc.alu.pipe_data import IntegerData
class CRInputData(IntegerData):
class CRInputData(IntegerData):
diff --git
a/src/soc/logical/pipe_data.py
b/src/soc/logical/pipe_data.py
index 34d9c0aea87c8af75b162b9b309ccda462855a3a..4bf064fe901a31f029c3f8eb0145c2f941a9c9a4 100644
(file)
--- a/
src/soc/logical/pipe_data.py
+++ b/
src/soc/logical/pipe_data.py
@@
-1,18
+1,6
@@
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
from nmigen import Signal, Const
from ieee754.fpcommon.getop import FPPipeContext
-
-
-class IntegerData:
-
- def __init__(self, pspec):
- self.ctx = FPPipeContext(pspec)
- self.muxid = self.ctx.muxid
-
- def __iter__(self):
- yield from self.ctx
-
- def eq(self, i):
- return [self.ctx.eq(i.ctx)]
+from soc.alu.pipe_data import IntegerData
class ALUInputData(IntegerData):
class ALUInputData(IntegerData):
diff --git
a/src/soc/shift_rot/pipe_data.py
b/src/soc/shift_rot/pipe_data.py
index 291ecf0aaf7547089a3b4801812337cd949e66fc..7f98d16b136f121c0c73b3e8cb81d44c8457dbcc 100644
(file)
--- a/
src/soc/shift_rot/pipe_data.py
+++ b/
src/soc/shift_rot/pipe_data.py
@@
-2,19
+2,7
@@
from nmigen import Signal, Const
from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.alu.alu_input_record import CompALUOpSubset
from ieee754.fpcommon.getop import FPPipeContext
from nmutil.dynamicpipe import SimpleHandshakeRedir
from soc.alu.alu_input_record import CompALUOpSubset
from ieee754.fpcommon.getop import FPPipeContext
-
-
-class IntegerData:
-
- def __init__(self, pspec):
- self.ctx = FPPipeContext(pspec)
- self.muxid = self.ctx.muxid
-
- def __iter__(self):
- yield from self.ctx
-
- def eq(self, i):
- return [self.ctx.eq(i.ctx)]
+from soc.alu.pipe_data import IntegerData
class ShiftRotInputData(IntegerData):
class ShiftRotInputData(IntegerData):