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remove debug prints
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 23 Jul 2019 16:30:01 +0000
(17:30 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 23 Jul 2019 16:30:01 +0000
(17:30 +0100)
src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
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src/ieee754/fpcommon/normtopack.py
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src/ieee754/fpcommon/test/fpmux.py
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src/ieee754/fpdiv/test/test_fpsqrt_pipe.py
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diff --git
a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 899f4f5e1d4c590de92ba2024a183d12740a48cf..438fc619711b385fef66fe5aa14021ca5ed871c0 100644
(file)
--- a/
src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/
src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@
-89,7
+89,7
@@
class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
def eq(self, rhs):
""" Assign member signals. """
def eq(self, rhs):
""" Assign member signals. """
- print (self, rhs)
+
#
print (self, rhs)
return DivPipeCoreInterstageData.eq(self, rhs) + \
DivPipeBaseData.eq(self, rhs)
return DivPipeCoreInterstageData.eq(self, rhs) + \
DivPipeBaseData.eq(self, rhs)
@@
-127,7
+127,7
@@
class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
def __init__(self, pspec):
self.pspec = pspec
def __init__(self, pspec):
self.pspec = pspec
- print ("DivPipeSetupStage", pspec, pspec.core_config)
+
#
print ("DivPipeSetupStage", pspec, pspec.core_config)
DivPipeCoreSetupStage.__init__(self, pspec.core_config)
def ispec(self):
DivPipeCoreSetupStage.__init__(self, pspec.core_config)
def ispec(self):
diff --git
a/src/ieee754/fpcommon/normtopack.py
b/src/ieee754/fpcommon/normtopack.py
index c78c1e95ed52a1b805a7dd7180a8b39b500ce207..b90d02321cfa1988fafe910a54ca0d4f03364656 100644
(file)
--- a/
src/ieee754/fpcommon/normtopack.py
+++ b/
src/ieee754/fpcommon/normtopack.py
@@
-18,7
+18,7
@@
class FPNormToPack(FPState, SimpleHandshake):
def __init__(self, pspec, e_extra=False):
FPState.__init__(self, "normalise_1")
def __init__(self, pspec, e_extra=False):
FPState.__init__(self, "normalise_1")
- print ("normtopack", pspec)
+
#
print ("normtopack", pspec)
self.pspec = pspec
self.e_extra = e_extra
SimpleHandshake.__init__(self, self) # pipeline is its own stage
self.pspec = pspec
self.e_extra = e_extra
SimpleHandshake.__init__(self, self) # pipeline is its own stage
diff --git
a/src/ieee754/fpcommon/test/fpmux.py
b/src/ieee754/fpcommon/test/fpmux.py
index f4f7253614bc4a07eabbee52f902f215fe7a4db4..a01ea3c9aa5b8165addf9ec351423cc7c21f12ae 100644
(file)
--- a/
src/ieee754/fpcommon/test/fpmux.py
+++ b/
src/ieee754/fpcommon/test/fpmux.py
@@
-161,7
+161,9
@@
def create_random(num_rows, width, single_op=False, n_vals=10):
#op1 = 0x1841
#op1 = 0x1841
+ # FSQRT
#op1 = 0x3449f9a9
#op1 = 0x3449f9a9
+ #op1 = 0x1ba94baa
vals.append((op1,))
else:
vals.append((op1,))
else:
diff --git
a/src/ieee754/fpdiv/test/test_fpsqrt_pipe.py
b/src/ieee754/fpdiv/test/test_fpsqrt_pipe.py
index 84cd4dadc86f7b4494dc272c75f8f902b97dd6cd..38b1f3609a0f0715a113c9844b6eda8a011ed3ee 100644
(file)
--- a/
src/ieee754/fpdiv/test/test_fpsqrt_pipe.py
+++ b/
src/ieee754/fpdiv/test/test_fpsqrt_pipe.py
@@
-12,17
+12,17
@@
def sqrt(x):
def test_pipe_sqrt_fp16():
dut = FPDIVMuxInOut(16, 4)
runfp(dut, 16, "test_fpsqrt_pipe_fp16", Float16, sqrt,
def test_pipe_sqrt_fp16():
dut = FPDIVMuxInOut(16, 4)
runfp(dut, 16, "test_fpsqrt_pipe_fp16", Float16, sqrt,
- single_op=True, opcode=1)
+ single_op=True, opcode=1
, n_vals=100
)
def test_pipe_sqrt_fp32():
dut = FPDIVMuxInOut(32, 4)
runfp(dut, 32, "test_fpsqrt_pipe_fp32", Float32, sqrt,
def test_pipe_sqrt_fp32():
dut = FPDIVMuxInOut(32, 4)
runfp(dut, 32, "test_fpsqrt_pipe_fp32", Float32, sqrt,
- single_op=True, opcode=1)
+ single_op=True, opcode=1
, n_vals=100
)
def test_pipe_sqrt_fp64():
dut = FPDIVMuxInOut(64, 4)
runfp(dut, 64, "test_fpsqrt_pipe_fp64", Float64, sqrt,
def test_pipe_sqrt_fp64():
dut = FPDIVMuxInOut(64, 4)
runfp(dut, 64, "test_fpsqrt_pipe_fp64", Float64, sqrt,
- single_op=True, opcode=1)
+ single_op=True, opcode=1
, n_vals=100
)
if __name__ == '__main__':
test_pipe_sqrt_fp16()
if __name__ == '__main__':
test_pipe_sqrt_fp16()