- endinterface
-
- module mkbus(Ifc_bus);
- Ifc_PintTop pintop <-mkPinTop;
- AXI4_Lite_Slave_Xactor_IFC#({0}, {1}, 0) slave_xactor <-
- mkAXI4_Lite_Slave_Xactor();
- rule read_transaction;
- let req<-pop_o(slave_xactor.o_rd_addr);
- let {{err,data}}=pintop.read(req.araddr);
- AXI4_Lite_Rd_Data#({0}, 0) r = AXI4_Lite_Rd_Data {{
- rresp: err?AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
- rdata: zeroExtend(data) , ruser: 0}};
- slave_xactor.i_rd_data.enq(r);
- endrule
+ interface GPIO_config#(32) bankA_config;
+ interface AXI4_Lite_Slave_IFC#({0},{1},{2}) bankA_slave;
+ interface GPIO_config#(15) bankB_config;
+ interface AXI4_Lite_Slave_IFC#({0},{1},{2}) bankB_slave;