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hack which happens to get fsqrt preliminarily working
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 23 Jul 2019 16:27:22 +0000
(17:27 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 23 Jul 2019 16:27:22 +0000
(17:27 +0100)
src/ieee754/fpdiv/div0.py
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diff --git
a/src/ieee754/fpdiv/div0.py
b/src/ieee754/fpdiv/div0.py
index 16a78c6e5b6eb7d01b14bb4f6f5de8c171d70a2e..32d0d17cc8e38b2193400734fc4f9502bb2f27c2 100644
(file)
--- a/
src/ieee754/fpdiv/div0.py
+++ b/
src/ieee754/fpdiv/div0.py
@@
-103,11
+103,11
@@
class FPDivStage0Mod(Elaboratable):
with m.Elif(self.i.ctx.op == 1):
am0 = Signal(len(self.i.a.m)+3, reset_less=True)
with m.If(self.i.a.e[0]):
with m.Elif(self.i.ctx.op == 1):
am0 = Signal(len(self.i.a.m)+3, reset_less=True)
with m.If(self.i.a.e[0]):
- m.d.comb += am0.eq(Cat(
0,0, self.i.a.m, 0
))
- m.d.comb += self.o.z.e.eq(((self.i.a.e+1) >> 1))
+ m.d.comb += am0.eq(Cat(
self.i.a.m, 0)<<(extra-2
))
+ m.d.comb += self.o.z.e.eq(((self.i.a.e+1) >> 1)
+1
)
with m.Else():
with m.Else():
- m.d.comb += am0.eq(Cat(0,
0, 0, self.i.a.m
))
- m.d.comb += self.o.z.e.eq((self.i.a.e >> 1))
+ m.d.comb += am0.eq(Cat(0,
self.i.a.m)<<(extra-2
))
+ m.d.comb += self.o.z.e.eq((self.i.a.e >> 1)
+1
)
m.d.comb += [self.o.z.s.eq(self.i.a.s),
self.o.divisor_radicand.eq(am0),
m.d.comb += [self.o.z.s.eq(self.i.a.s),
self.o.divisor_radicand.eq(am0),