+def regfile_array_sim(dut, rp1, rp2, wp):
+ yield wp.data_i.eq(2)
+ yield wp.wen.eq(1<<1)
+ yield
+ yield wp.wen.eq(0)
+ yield rp1.ren.eq(1<<1)
+ yield
+ data = yield rp1.data_o
+ print (data)
+ assert data == 2
+
+ yield rp1.ren.eq(1<<5)
+ yield rp2.ren.eq(1<<1)
+ yield wp.wen.eq(1<<5)
+ yield wp.data_i.eq(6)
+ data = yield rp1.data_o
+ print (data)
+ yield
+ yield wp.wen.eq(0)
+ yield rp1.ren.eq(0)
+ yield rp2.ren.eq(0)
+ data1 = yield rp1.data_o
+ print (data1)
+ data2 = yield rp2.data_o
+ print (data2)
+ assert data1 == 6
+ yield
+ data = yield rp1.data_o
+ print (data)
+