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add a jk latch (as a comment), TODO
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 11 May 2019 04:12:38 +0000
(
05:12
+0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 11 May 2019 04:24:08 +0000
(
05:24
+0100)
src/nmutil/latch.py
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diff --git
a/src/nmutil/latch.py
b/src/nmutil/latch.py
index a334f6671f819449739d6cea8b8f1bd191a5a5f9..d845a954331be955681adac188d7e4f05c9ba4b5 100644
(file)
--- a/
src/nmutil/latch.py
+++ b/
src/nmutil/latch.py
@@
-2,6
+2,24
@@
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
from nmigen import Signal, Module, Elaboratable
from nmigen.cli import verilog, rtlil
from nmigen import Signal, Module, Elaboratable
+""" jk latch
+
+module jk(q,q1,j,k,c);
+output q,q1;
+input j,k,c;
+reg q,q1;
+initial begin q=1'b0; q1=1'b1; end
+always @ (posedge c)
+ begin
+ case({j,k})
+ {1'b0,1'b0}:begin q=q; q1=q1; end
+ {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
+ {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
+ {1'b1,1'b1}: begin q=~q; q1=~q1; end
+ endcase
+ end
+endmodule
+"""
class SRLatch(Elaboratable):
def __init__(self, sync=True):
class SRLatch(Elaboratable):
def __init__(self, sync=True):