+# "State" Regfile
+class StateRegs(RegFileArray):
+ """StateRegs
+
+ State regfile - PC, MSR and later SimpleV VL
+
+ * QTY 2of 64-bit registers
+ * 3R2W
+ * Array-based unary-indexed (not binary-indexed)
+ * write-through capability (read on same cycle as write)
+
+ Note: d_wr1 d_rd1 are for use by the decoder, to get at the PC.
+ will probably have to also add one so it can get at the MSR as well.
+ (d_rd2)
+ """
+ PC = 0
+ MSR = 1
+ def __init__(self):
+ super().__init__(64, 2)
+ self.w_ports = {'nia': self.write_port("nia"),
+ 'msr': self.write_port("msr"),
+ 'd_wr1': self.write_port("d_wr1")} # writing PC (issuer)
+ self.r_ports = {'cia': self.read_port("cia"), # reading PC (issuer)
+ 'msr': self.read_port("msr"), # reading MSR (issuer)
+ }
+
+