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re-add CRG (clock reset generator)
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 22 Jul 2020 21:11:57 +0000
(22:11 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Wed, 22 Jul 2020 21:11:57 +0000
(22:11 +0100)
src/soc/litex/sim.py
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diff --git
a/src/soc/litex/sim.py
b/src/soc/litex/sim.py
index 8707ba000b16f27a8989b08820a1bd0b9c0f2701..3c3dcbae0ae27c13f08b3c7eb95c608752692790 100644
(file)
--- a/
src/soc/litex/sim.py
+++ b/
src/soc/litex/sim.py
@@
-7,10
+7,9
@@
import os
import argparse
import os
import argparse
-from migen import ClockDomain
-
from litex.build.generic_platform import Pins, Subsignal
from litex.build.sim import SimPlatform
from litex.build.generic_platform import Pins, Subsignal
from litex.build.sim import SimPlatform
+from litex.build.io import CRG
from litex.build.sim.config import SimConfig
from litex.soc.integration.soc import SoCRegion
from litex.build.sim.config import SimConfig
from litex.soc.integration.soc import SoCRegion
@@
-76,11
+75,8
@@
class SoCSMP(SoCCore):
self.platform.name = "sim"
self.add_constant("SIM")
self.platform.name = "sim"
self.add_constant("SIM")
- self.clock_domains.cd_sys = ClockDomain()
- self.comb += [
- self.cd_sys.clk.eq(platform.request("sys_clk")),
- self.cd_sys.rst.eq(platform.request("sys_rst"))
- ]
+ # CRG -------------------------------------------------------
+ self.submodules.crg = CRG(platform.request("sys_clk"))
# SDRAM ----------------------------------------------------------
phy_settings = get_sdram_phy_settings(
# SDRAM ----------------------------------------------------------
phy_settings = get_sdram_phy_settings(