+ dc = rcell[rn]
+ # accumulate cell inputs dest/src1/src2
+ dest_i.append(dc.dest_i)
+ src1_i.append(dc.src1_i)
+ src2_i.append(dc.src2_i)
+ # wire up inputs from module to row cell inputs (Cat is gooood)
+ m.d.comb += [Cat(*dest_i).eq(self.dest_i),
+ Cat(*src1_i).eq(self.src1_i),
+ Cat(*src2_i).eq(self.src2_i),
+ ]
+
+ # ---
+ # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
+ # ---
+ go_rd_i = []
+ go_wr_i = []
+ issue_i = []
+ for rn in range(self.n_reg_col):
+ dc = rcell[rn]
+ # accumulate cell outputs for issue/go_rd/go_wr
+ go_rd_i.append(dc.go_rd_i)
+ go_wr_i.append(dc.go_wr_i)
+ issue_i.append(dc.issue_i)
+ # wire up inputs from module to row cell inputs (Cat is gooood)
+ m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
+ Cat(*go_wr_i).eq(self.go_wr_i),
+ Cat(*issue_i).eq(self.issue_i),
+ ]
+