- # Go through all ways in the set
- for i in range(self.way_count):
- # Pull out read port for readability
- read_port = self.read_port_array[i]
- with m.If(read_port.data[0]):
- # Pull out lru state for readability
- lru_state = read_port.data[self.data_start:self.data_end]
- # Pull out write port for readability
- write_port = self.write_port_array[i]
- # Enable write for the memory block
- m.d.comb += write_port.en.eq(1)
- with m.If(i == self.encoder.o):
- m.d.comb += write_port.data.eq(0)
- with m.Elif(state < self.way_count):
- m.d.comb += write_port.data.eq(state + 1)
- with m.Else():
- m.d.comb += write_port.data.eq(state)
+ # Pull out the set's entry being edited
+ plru_entry = self.plru_array[self.cset]
+ m.d.comb += [
+ # Set the plru data to the current state
+ self.plru.plru_tree.eq(plru_entry),
+ # Set what entry was just hit
+ self.plru.lu_hit.eq(self.encoder.o),
+ # Set that the cache was accessed
+ self.plru.lu_access_i.eq(1)
+ ]