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add extra FSM explanatory comments to TestIssuer
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 14 Feb 2021 12:34:38 +0000
(12:34 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 14 Feb 2021 12:34:38 +0000
(12:34 +0000)
src/soc/simple/issuer.py
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diff --git
a/src/soc/simple/issuer.py
b/src/soc/simple/issuer.py
index ad9b1dd7127b6afa81a117f7ba594004621631d6..8c69b1150702a8acbe968e32cf92a8d1d9942488 100644
(file)
--- a/
src/soc/simple/issuer.py
+++ b/
src/soc/simple/issuer.py
@@
-260,6
+260,11
@@
class TestIssuerInternal(Elaboratable):
# then "holds" information, combinatorially, for the core
# (as opposed to using sync - which would be on a clock's delay)
# this includes the actual opcode, valid flags and so on.
# then "holds" information, combinatorially, for the core
# (as opposed to using sync - which would be on a clock's delay)
# this includes the actual opcode, valid flags and so on.
+
+ # this FSM performs fetch of raw instruction data, partial-decodes
+ # it 32-bit at a time to detect SVP64 prefixes, and will optionally
+ # read a 2nd 32-bit quantity if that occurs.
+
with m.FSM(name='fetch_fsm'):
# waiting (zzz)
with m.FSM(name='fetch_fsm'):
# waiting (zzz)
@@
-335,7
+340,11
@@
class TestIssuerInternal(Elaboratable):
with m.If(fetch_insn_ready_i):
m.next = "IDLE"
with m.If(fetch_insn_ready_i):
m.next = "IDLE"
- # decode / issue / execute FSM
+ # decode / issue / execute FSM. this interacts with the "fetch" FSM
+ # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
+ # (outgoing). SVP64 RM prefixes have already been set up by the
+ # "fetch" phase, so execute is fairly straightforward.
+
with m.FSM():
# go fetch the instruction at the current PC
with m.FSM():
# go fetch the instruction at the current PC