# test with MMU
from openpower.test.mmu.mmu_cases import MMUTestCase
from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
# test with MMU
from openpower.test.mmu.mmu_cases import MMUTestCase
from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
self.add_case(Program(lst, bigendian), initial_regs,
initial_mem=initial_mem)
self.add_case(Program(lst, bigendian), initial_regs,
initial_mem=initial_mem)
def case_2_tlbie(self):
lst = ["tlbie 1,1,1,1,1"] # tlbie RB,RS,RIC,PRS,R
initial_regs = [0] * 32
def case_2_tlbie(self):
lst = ["tlbie 1,1,1,1,1"] # tlbie RB,RS,RIC,PRS,R
initial_regs = [0] * 32
self.add_case(Program(lst, bigendian), initial_regs,
initial_mem=initial_mem)
self.add_case(Program(lst, bigendian), initial_regs,
initial_mem=initial_mem)
self.add_case(Program(lst, bigendian), initial_regs,
initial_mem=initial_mem)
self.add_case(Program(lst, bigendian), initial_regs,
initial_mem=initial_mem)
def case_4_mfspr(self):
lst = ["mfspr 1,18", # mtspr r1,DSISR
"mfspr 2,19"] # mtspr r2,DAR
def case_4_mfspr(self):
lst = ["mfspr 1,18", # mtspr r1,DSISR
"mfspr 2,19"] # mtspr r2,DAR
# MMU/DCache integration tests
suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
# MMU/DCache integration tests
suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,