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re-enable shadow/go_die
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 23 May 2019 08:58:14 +0000
(09:58 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 23 May 2019 08:58:14 +0000
(09:58 +0100)
src/experiment/compalu.py
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diff --git
a/src/experiment/compalu.py
b/src/experiment/compalu.py
index 74489360d1a3a10dc892471781515110a2dc03d3..bcd71b0cabc63d54565e5f21217ef488ae5f943c 100644
(file)
--- a/
src/experiment/compalu.py
+++ b/
src/experiment/compalu.py
@@
-69,10
+69,8
@@
class ComputationUnitNoDelay(Elaboratable):
# shadow/go_die
reset_w = Signal(reset_less=True)
reset_r = Signal(reset_less=True)
# shadow/go_die
reset_w = Signal(reset_less=True)
reset_r = Signal(reset_less=True)
- #m.d.comb += reset_w.eq(self.go_wr_i)# | self.go_die_i)
- #m.d.comb += reset_r.eq(self.go_rd_i)# | self.go_die_i)
- reset_w = self.go_wr_i
- reset_r = self.go_rd_i
+ m.d.comb += reset_w.eq(self.go_wr_i | self.go_die_i)
+ m.d.comb += reset_r.eq(self.go_rd_i | self.go_die_i)
# This is fascinating and very important to observe that this
# is in effect a "3-way revolving door". At no time may all 3
# This is fascinating and very important to observe that this
# is in effect a "3-way revolving door". At no time may all 3
@@
-98,6
+96,8
@@
class ComputationUnitNoDelay(Elaboratable):
m.d.comb += self.busy_o.eq(opc_l.q) # busy out
m.d.comb += self.rd_rel_o.eq(src_l.q & opc_l.q) # src1/src2 req rel
m.d.comb += self.busy_o.eq(opc_l.q) # busy out
m.d.comb += self.rd_rel_o.eq(src_l.q & opc_l.q) # src1/src2 req rel
+ # the counter is just for demo purposes, to get the ALUs of different
+ # types to take arbitrary completion times
with m.If(opc_l.qn):
m.d.sync += self.counter.eq(0)
with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
with m.If(opc_l.qn):
m.d.sync += self.counter.eq(0)
with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
@@
-111,7
+111,7
@@
class ComputationUnitNoDelay(Elaboratable):
m.d.sync += self.counter.eq(self.counter - 1)
with m.If(self.counter == 1):
# write req release out. waits until shadow is dropped.
m.d.sync += self.counter.eq(self.counter - 1)
with m.If(self.counter == 1):
# write req release out. waits until shadow is dropped.
- m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q
)#
& self.shadown_i)
+ m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q & self.shadown_i)
# create a latch/register for src1/src2
latchregister(m, self.src1_i, self.alu.a, src_l.q)
# create a latch/register for src1/src2
latchregister(m, self.src1_i, self.alu.a, src_l.q)