start wiring TestCachedMemoryPortInterface

diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py
index 3a17749f80963e5cccb31ca3f5ba46256f9593e9..354730789112f3d4cb1183091216a793c5d6a1fe 100644 (file)
--- a/src/soc/experiment/test/test_l0_cache_buffer2.py
+++ b/src/soc/experiment/test/test_l0_cache_buffer2.py
@@ -3,7 +3,7 @@ test cases for LDSTSplitter and L0CacheBuffer2
 """
 
 from soc.experiment.l0_cache import L0CacheBuffer2
 """
 
 from soc.experiment.l0_cache import L0CacheBuffer2

-from nmigen import Module
+from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const

 from nmigen.cli import rtlil
 from soc.scoreboard.addr_split import LDSTSplitter
 from soc.scoreboard.addr_match import LenExpand
 from nmigen.cli import rtlil
 from soc.scoreboard.addr_split import LDSTSplitter
 from soc.scoreboard.addr_match import LenExpand


@@ -18,20 +18,22 @@ class TestCachedMemoryPortInterface(PortInterfaceBase):
     """TestCacheMemoryPortInterface
 
     This is a test class for simple verification of LDSTSplitter
     """TestCacheMemoryPortInterface
 
     This is a test class for simple verification of LDSTSplitter

-    conforming to PortInterface,
+    conforming to PortInterface

     """
 
     def __init__(self, regwid=64, addrwid=4):
         super().__init__(regwid, addrwid)
     """
 
     def __init__(self, regwid=64, addrwid=4):
         super().__init__(regwid, addrwid)

-        #self.ldst = LDSTSplitter()
+        self.ldst = LDSTSplitter(32, 48, 4)
+
+    # TODO implement these

 
     def set_wr_addr(self, m, addr, mask):
         lsbaddr, msbaddr = self.splitaddr(addr)
 
     def set_wr_addr(self, m, addr, mask):
         lsbaddr, msbaddr = self.splitaddr(addr)

-        #m.d.comb += self.mem.wrport.addr.eq(msbaddr)
+        #m.d.comb += self.ldst... ### .eq(msbaddr)

 
     def set_rd_addr(self, m, addr, mask):
         lsbaddr, msbaddr = self.splitaddr(addr)
 
     def set_rd_addr(self, m, addr, mask):
         lsbaddr, msbaddr = self.splitaddr(addr)

-        #m.d.comb += self.mem.rdport.addr.eq(msbaddr)
+        #m.d.comb += self..eq(msbaddr)

 
     def set_wr_data(self, m, data, wen):
         #m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 
     def set_wr_data(self, m, data, wen):
         #m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem


@@ -39,8 +41,7 @@ class TestCachedMemoryPortInterface(PortInterfaceBase):
         return Const(1, 1) #document return value
 
     def get_rd_data(self, m):
         return Const(1, 1) #document return value
 
     def get_rd_data(self, m):

-        #return self.mem.rdport.data, Const(1, 1)
-        return None 
+        return self.ldst.ld_data_o.data, Const(1, 1)

 
     def elaborate(self, platform):
         m = super().elaborate(platform)
 
     def elaborate(self, platform):
         m = super().elaborate(platform)

diff --git a/src/soc/scoreboard/addr_split.py b/src/soc/scoreboard/addr_split.py
index 4a9573382cdcf5bbb280a9450e4591ca8df8c795..3d197f2e9daffabccce04d9b136d0d86b01e4b90 100644 (file)
--- a/src/soc/scoreboard/addr_split.py
+++ b/src/soc/scoreboard/addr_split.py
@@ -6,7 +6,7 @@ Links:
 * http://bugs.libre-riscv.org/show_bug.cgi?id=216
 """
 
 * http://bugs.libre-riscv.org/show_bug.cgi?id=216
 """
 

-from soc.experiment.pimem import PortInterface
+#from soc.experiment.pimem import PortInterface

 
 from nmigen import Elaboratable, Module, Signal, Record, Array, Const, Cat
 from nmutil.latch import SRLatch, latchregister
 
 from nmigen import Elaboratable, Module, Signal, Record, Array, Const, Cat
 from nmutil.latch import SRLatch, latchregister


@@ -80,19 +80,14 @@ class LDSTSplitter(Elaboratable):
         # cline_wid = 8<<dlen # cache line width: bytes (8) times (2^^dlen)
         cline_wid = dwidth*8  # convert bytes to bits
 
         # cline_wid = 8<<dlen # cache line width: bytes (8) times (2^^dlen)
         cline_wid = dwidth*8  # convert bytes to bits
 

-        if(pi is None):
-            self.pi = PortInterface()
-        else:
-            self.pi = pi
-
-        self.addr_i = self.pi.addr.data  #Signal(awidth, reset_less=True)
+        self.addr_i = Signal(awidth, reset_less=True)

         # no match in PortInterface
         self.len_i = Signal(dlen, reset_less=True)
         self.valid_i = Signal(reset_less=True)
         self.valid_o = Signal(reset_less=True)
 
         # no match in PortInterface
         self.len_i = Signal(dlen, reset_less=True)
         self.valid_i = Signal(reset_less=True)
         self.valid_o = Signal(reset_less=True)
 

-        self.is_ld_i = self.pi.is_ld_i #Signal(reset_less=True)
-        self.is_st_i = self.pi.is_st_i #Signal(reset_less=True)
+        self.is_ld_i = Signal(reset_less=True)
+        self.is_st_i = Signal(reset_less=True)

 
         self.ld_data_o = LDData(dwidth*8, "ld_data_o") #port.ld
         self.st_data_i = LDData(dwidth*8, "st_data_i") #port.st
 
         self.ld_data_o = LDData(dwidth*8, "ld_data_o") #port.ld
         self.st_data_i = LDData(dwidth*8, "st_data_i") #port.st


@@ -120,6 +115,10 @@ class LDSTSplitter(Elaboratable):
         m.submodules.ld2 = ld2 = LDLatch(self.dwidth*8, self.awidth-dlen, mlen)
         m.submodules.lenexp = lenexp = LenExpand(self.dlen)
 
         m.submodules.ld2 = ld2 = LDLatch(self.dwidth*8, self.awidth-dlen, mlen)
         m.submodules.lenexp = lenexp = LenExpand(self.dlen)
 

+        #comb += self.pi.addr_ok_o.eq(self.addr_i < 65536) #FIXME 64k limit
+        #comb += self.pi.busy_o.eq(busy)
+
+

         # FIXME bytes not bits
         # set up len-expander, len to mask.  ld1 gets first bit, ld2 gets rest
         comb += lenexp.addr_i.eq(self.addr_i)
         # FIXME bytes not bits
         # set up len-expander, len to mask.  ld1 gets first bit, ld2 gets rest
         comb += lenexp.addr_i.eq(self.addr_i)


@@ -127,7 +126,7 @@ class LDSTSplitter(Elaboratable):
         mask1 = Signal(mlen, reset_less=True)
         mask2 = Signal(mlen, reset_less=True)
         comb += mask1.eq(lenexp.lexp_o[0:mlen])  # Lo bits of expanded len-mask
         mask1 = Signal(mlen, reset_less=True)
         mask2 = Signal(mlen, reset_less=True)
         comb += mask1.eq(lenexp.lexp_o[0:mlen])  # Lo bits of expanded len-mask

-        comb += mask2.eq(lenexp.lexp_o[mlen:])  # Hi bits of expanded len-mask
+        comb += mask2.eq(lenexp.lexp_o[mlen:])   # Hi bits of expanded len-mask

 
         # set up new address records: addr1 is "as-is", addr2 is +1
         comb += ld1.addr_i.eq(self.addr_i[dlen:])
 
         # set up new address records: addr1 is "as-is", addr2 is +1
         comb += ld1.addr_i.eq(self.addr_i[dlen:])


@@ -177,6 +176,7 @@ class LDSTSplitter(Elaboratable):
                                                (ld2.ld_o.data << (ashift2*8)))
 
         with m.If(self.is_st_i):
                                                (ld2.ld_o.data << (ashift2*8)))
 
         with m.If(self.is_st_i):

+            # set busy flag -- required for unit test

             for i, (ld, mask) in enumerate(((ld1, mask1),
                                             (ld2, mask2))):
                 valid = Signal(name="stvalid_i%d" % i, reset_less=True)
             for i, (ld, mask) in enumerate(((ld1, mask1),
                                             (ld2, mask2))):
                 valid = Signal(name="stvalid_i%d" % i, reset_less=True)