+ # For-loop for testing output enable signals
+ for gpio_o_val in range(0, num_gpio_o_states):
+ yield top.gpio_oe_test.eq(gpio_o_val)
+ yield # Move to the next clk cycle
+
+ for gpio_bit in range(0, num_gpios):
+ pad_oe[gpio_bit] = yield gpio_pad_oe[gpio_bit]
+ yield
+
+ for gpio_bit in range(0, num_gpios):
+ oe_test_bit = ((gpio_o_val & (1 << gpio_bit)) != 0)
+ # oe set at core matches oe seen at pad:
+ assert oe_test_bit == pad_oe[gpio_bit]
+ # For debugging - VERY verbose
+ #print("---------------------")
+ #print("Test Output Enable: ", bin(gpio_o_val))
+ # Print MSB first
+ #print("Pad Output Enable: ", list(reversed(pad_oe)))
+ #print("---------------------")
+ print("GPIO Test PASSED!")
+
+
+def test_debug_print():
+ print("Test used for getting object methods/information")
+ print("Moved here to clear clutter of gpio test")
+
+ print ("printing out info about the resource gpio0")
+ print (top.gpio['gpio0']['i'])
+ print ("this is a PIN resource", type(top.gpio['gpio0']['i']))
+ # yield can only be done on SIGNALS or RECORDS,
+ # NOT Pins/Resources gpio0_core_in = yield top.gpio['gpio0']['i']
+ print("Test gpio0 core in: ", gpio0_core_in)
+
+ print("JTAG")
+ print(top.jtag.__class__.__name__, dir(top.jtag))
+ print("TOP")
+ print(top.__class__.__name__, dir(top))
+ print("PORT")
+ print(top.ports.__class__.__name__, dir(top.ports))
+ print("GPIO")
+ print(top.gpio.__class__.__name__, dir(top.gpio))
+
+ # Trying to read input from core side, looks like might be a pin...
+ # XXX don't "look like" - don't guess - *print it out*
+ #print ("don't guess, CHECK", type(top.gpio.gpio0.i))
+
+ print () # extra print to divide the output