IDLE = 0 # ready for instruction
ACK_WAIT = 1 # waiting for ack from dcache
MMU_LOOKUP = 2 # waiting for MMU to look up translation
IDLE = 0 # ready for instruction
ACK_WAIT = 1 # waiting for ack from dcache
MMU_LOOKUP = 2 # waiting for MMU to look up translation
# exception thrown, clear out instruction fault state
sync += self.r_instr_fault.eq(0)
# exception thrown, clear out instruction fault state
sync += self.r_instr_fault.eq(0)
# MMU FSM communicating a request to update DSISR or DAR (OP_MTSPR)
with m.If(self.mmu_set_spr):
with m.If(self.mmu_set_dsisr):
# MMU FSM communicating a request to update DSISR or DAR (OP_MTSPR)
with m.If(self.mmu_set_spr):
with m.If(self.mmu_set_dsisr):