-
-def i2s(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- i2spins = ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
- # for i in range(4):
- # i2spins.append("DO%d+" % i)
- return Pins('IIS', i2spins, bankspec, suffix, offs, bank, mux, spec, limit,
- origsuffix=suffix)
-
-
-def emmc(bankspec, suffix, offs, bank, mux=1, spec=None):
- emmcpins = ['CMD+', 'CLK+']
- for i in range(8):
- emmcpins.append("D%d*" % i)
- return Pins('MMC', emmcpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def sdmmc(bankspec, suffix, offs, bank, mux=1, spec=None,
- start=None, limit=None):
- sdmmcpins = ['CMD+', 'CLK+']
- for i in range(4):
- sdmmcpins.append("D%d*" % i)
- sdmmcpins = sdmmcpins[start:limit]
- return Pins('SD', sdmmcpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def spi(bankspec, suffix, offs, bank, mux=1, spec=None):
- spipins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
- return Pins('SPI', spipins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def quadspi(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- spipins = ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
- return Pins(
- 'QSPI',
- spipins,
- bankspec,
- suffix,
- offs,
- bank,
- mux,
- spec,
- limit,
- origsuffix=suffix)
-
-
-def i2c(bankspec, suffix, offs, bank, mux=1, spec=None):
- spipins = ['SDA*', 'SCL*']
- return Pins('TWI', spipins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def jtag(bankspec, suffix, offs, bank, mux=1, spec=None):
- jtagpins = ['MS+', 'DI-', 'DO+', 'CK+']
- return Pins('JTAG', jtagpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def uart(bankspec, suffix, offs, bank, mux=1, spec=None):
- uartpins = ['TX+', 'RX-']
- return Pins('UART', uartpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def namesuffix(name, suffix, namelist):
- names = []
- for n in namelist:
- if n:
- names.append("%s%s_%s" % (name, suffix, n))
- else:
- names.append("%s_%s" % (name, suffix))
- return names
-
-
-def ulpi(bankspec, suffix, offs, bank, mux=1, spec=None):
- ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+']
- for i in range(8):
- ulpipins.append('D%d*' % i)
- return Pins('ULPI', ulpipins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def uartfull(bankspec, suffix, offs, bank, mux=1, spec=None):
- uartpins = ['TX+', 'RX-', 'CTS-', 'RTS+']
- return Pins('UARTQ', uartpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def rgbttl(bankspec, suffix, offs, bank, mux=1, spec=None):
- ttlpins = ['CK+', 'DE+', 'HS+', 'VS+']
- for i in range(24):
- ttlpins.append("D%d+" % i)
- return Pins('LCD', ttlpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def rgmii(bankspec, suffix, offs, bank, mux=1, spec=None):
- buspins = []
- for i in range(4):
- buspins.append("ERXD%d-" % i)
- for i in range(4):
- buspins.append("ETXD%d+" % i)
- buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-',
- 'EMDC+', 'EMDIO*',
- 'ETXEN+', 'ETXCK+', 'ECRS-',
- 'ECOL+', 'ETXERR+']
- return Pins('RG', buspins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def flexbus1(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- buspins = []
- for i in range(8):
- buspins.append("AD%d*" % i)
- for i in range(2):
- buspins.append("CS%d+" % i)
- buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+',
- 'A0', 'A1', 'TS', 'TBST',
- 'TSIZ0', 'TSIZ1']
- for i in range(4):
- buspins.append("BWE%d" % i)
- for i in range(2, 6):
- buspins.append("CS%d+" % i)
- return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
- origsuffix=suffix)
-
-
-def flexbus2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- buspins = []
- for i in range(8, 32):
- buspins.append("AD%d*" % i)
- return Pins('FB', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
- origsuffix=suffix)
-
-
-def sdram1(bankspec, suffix, offs, bank, mux=1, spec=None):
- buspins = []
- for i in range(16):
- buspins.append("SDRDQM%d*" % i)
- for i in range(12):
- buspins.append("SDRAD%d+" % i)
- for i in range(8):
- buspins.append("SDRDQ%d+" % i)
- for i in range(3):
- buspins.append("SDRCS%d#+" % i)
- for i in range(2):
- buspins.append("SDRDQ%d+" % i)
- for i in range(2):
- buspins.append("SDRBA%d+" % i)
- buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
- 'SDRRST+']
- return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def sdram2(bankspec, suffix, offs, bank, mux=1, spec=None, limit=None):
- buspins = []
- for i in range(3, 6):
- buspins.append("SDRCS%d#+" % i)
- for i in range(8, 32):
- buspins.append("SDRDQ%d*" % i)
- return Pins('SDR', buspins, bankspec, suffix, offs, bank, mux, spec, limit,
- origsuffix=suffix)
-
-
-def mcu8080(bankspec, suffix, offs, bank, mux=1, spec=None):
- buspins = []
- for i in range(8):
- buspins.append("MCUD%d*" % i)
- for i in range(8):
- buspins.append("MCUAD%d+" % (i + 8))
- for i in range(6):
- buspins.append("MCUCS%d+" % i)
- for i in range(2):
- buspins.append("MCUNRB%d+" % i)
- buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
- 'MCURST+']
- return Pins('MCU', buspins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def _pinbank(bankspec, prefix, suffix, offs, bank, gpiooffs, gpionum=1, mux=1,
- spec=None):
- gpiopins = []
- for i in range(gpiooffs, gpiooffs + gpionum):
- gpiopins.append("%s%d*" % (bank, i))
- return Pins(prefix, gpiopins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def eint(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
- gpiopins = []
- for i in range(gpiooffs, gpiooffs + gpionum):
- gpiopins.append("%d*" % (i))
- return Pins('EINT', gpiopins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def pwm(bankspec, suffix, offs, bank, pwmoffs, pwmnum=1, mux=1, spec=None):
- pwmpins = []
- for i in range(pwmoffs, pwmoffs + pwmnum):
- pwmpins.append("%d+" % (i))
- return Pins('PWM', pwmpins, bankspec, suffix, offs, bank, mux, spec,
- origsuffix=suffix)
-
-
-def gpio(bankspec, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None):
- return _pinbank(bankspec, "GPIO%s" % bank, suffix, offs, bank, gpiooffs,
- gpionum, mux=0, spec=None)
-
-
-def pinmerge(pins, fn):
- # hack, store the function specs in the pins dict
- fname = fn.fname
- suffix = fn.origsuffix
- bank = fn.bank
-
- if not hasattr(pins, 'fnspec'):
- pins.fnspec = pins
- if fname == 'GPIO':
- fname = fname + bank
- assert 'EINT' not in pins
- if fname not in pins.fnspec:
- pins.add_spec(fname, {})
- if suffix or fname == 'EINT' or fname == 'PWM':
- specname = fname + suffix
- else:
- specname = fname
- print "fname bank specname suffix ", fname, bank, specname, repr(suffix)
- if specname in pins.fnspec[fname]:
- # ok so some declarations may bring in different
- # names at different stages (EINT, PWM, flexbus1/2)
- # so we have to merge the names in. main thing is
- # the pingroup
- tomerge = pins.fnspec[fname][specname]
- for p in fn.pingroup:
- if p not in tomerge.pingroup:
- tomerge.pingroup.append(p)
- tomerge.pins.update(fn.pins)
- tomerge.fntype.update(fn.fntype)
- else:
- pins.fnspec[fname][specname] = deepcopy(fn)
-
- # merge actual pins
- for (pinidx, v) in fn.pins.items():
- pins.update(pinidx, v)