# set up Integer Function Unit, add to module (and python list)
fu = IntFnUnit(self.n_regs, shadow_wid=0)
setattr(m.submodules, "intfu%d" % i, fu)
# set up Integer Function Unit, add to module (and python list)
fu = IntFnUnit(self.n_regs, shadow_wid=0)
setattr(m.submodules, "intfu%d" % i, fu)
# collate the read/write pending vectors (to go into global pending)
int_src1_pend_v.append(fu.src1_pend_o)
int_src2_pend_v.append(fu.src2_pend_o)
int_rd_pend_v.append(fu.int_rd_pend_o)
int_wr_pend_v.append(fu.int_wr_pend_o)
# collate the read/write pending vectors (to go into global pending)
int_src1_pend_v.append(fu.src1_pend_o)
int_src2_pend_v.append(fu.src2_pend_o)
int_rd_pend_v.append(fu.int_rd_pend_o)
int_wr_pend_v.append(fu.int_wr_pend_o)
fn_issue_l.append(fu.issue_i)
fn_busy_l.append(fu.busy_o)
m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
fn_issue_l.append(fu.issue_i)
fn_busy_l.append(fu.busy_o)
m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
- m.d.comb += il[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd
- m.d.comb += il[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr
+ m.d.sync += if_l[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd
+ m.d.comb += if_l[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr
- m.d.comb += il[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
- m.d.comb += il[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
+ m.d.sync += if_l[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
+ m.d.comb += if_l[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
# Connect Picker
#---------
m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
# Connect Picker
#---------
m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
- m.d.sync += intpick1.readable_i[0].eq(il[0].int_readable_o) # add rdable
- m.d.comb += intpick1.writable_i[0].eq(il[0].int_writable_o) # add rdable
- m.d.sync += intpick1.readable_i[1].eq(il[1].int_readable_o) # sub rdable
- m.d.comb += intpick1.writable_i[1].eq(il[1].int_writable_o) # sub rdable
+ m.d.comb += intpick1.readable_i[0].eq(if_l[0].int_readable_o) # add rd
+ m.d.comb += intpick1.writable_i[0].eq(if_l[0].int_writable_o) # add wr
+ m.d.comb += intpick1.readable_i[1].eq(if_l[1].int_readable_o) # sub rd
+ m.d.comb += intpick1.writable_i[1].eq(if_l[1].int_writable_o) # sub wr
- m.d.comb += alu.go_rd_i.eq(il[i].go_rd_i) # chained from intpick
- m.d.comb += alu.go_wr_i.eq(il[i].go_wr_i) # chained from intpick
+ m.d.comb += alu.go_rd_i.eq(if_l[i].go_rd_i) # chained from intpick
+ m.d.comb += alu.go_wr_i.eq(if_l[i].go_wr_i) # chained from intpick
m.d.comb += alu.issue_i.eq(fn_issue_l[i])
#m.d.comb += fn_busy_l[i].eq(alu.busy_o) # XXX ignore, use fnissue
m.d.comb += alu.src1_i.eq(int_src1.data_o)
m.d.comb += alu.src2_i.eq(int_src2.data_o)
m.d.comb += alu.issue_i.eq(fn_issue_l[i])
#m.d.comb += fn_busy_l[i].eq(alu.busy_o) # XXX ignore, use fnissue
m.d.comb += alu.src1_i.eq(int_src1.data_o)
m.d.comb += alu.src2_i.eq(int_src2.data_o)
yield from int_instr(dut, IADD, 5, 2, 5)
yield from print_reg(dut, [3,4,5])
yield
yield from int_instr(dut, IADD, 5, 2, 5)
yield from print_reg(dut, [3,4,5])
yield
- yield from int_instr(dut, ISUB, 5, 2, 3)
+ yield from int_instr(dut, ISUB, 5, 1, 3)
yield from print_reg(dut, [3,4,5])
yield
yield from print_reg(dut, [3,4,5])
yield from print_reg(dut, [3,4,5])
yield
yield from print_reg(dut, [3,4,5])