from soc.regfile.virtual_port import VirtualRegPort
from openpower.decoder.power_enums import SPRfull, SPRreduced
from soc.regfile.virtual_port import VirtualRegPort
from openpower.decoder.power_enums import SPRfull, SPRreduced
self.w_ports = {'nia': self.write_port("nia"),
'msr': self.write_port("msr"),
'sv': self.write_port("sv"), # writing SVSTATE (issuer)
self.w_ports = {'nia': self.write_port("nia"),
'msr': self.write_port("msr"),
'sv': self.write_port("sv"), # writing SVSTATE (issuer)
"""FastRegs
FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC
"""FastRegs
FAST regfile - CTR, LR, TAR, SRR1, SRR2, XER, TB, DEC
self.w_ports = {'fast1': self.write_port("dest1"),
'issue': self.write_port("issue"), # writing DEC/TB
}
self.w_ports = {'fast1': self.write_port("dest1"),
'issue': self.write_port("issue"), # writing DEC/TB
}
"""XER Registers (SO, CA/CA32, OV/OV32)
* QTY 3of 2-bit registers
"""XER Registers (SO, CA/CA32, OV/OV32)
* QTY 3of 2-bit registers
self.w_ports = {'full_xer': self.full_wr, # 6-bit (masked, 3-en lines)
'xer_so': self.write_port("dest1"),
'xer_ca': self.write_port("dest2"),
self.w_ports = {'full_xer': self.full_wr, # 6-bit (masked, 3-en lines)
'xer_so': self.write_port("dest1"),
'xer_ca': self.write_port("dest2"),