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update MMU PortInterface Test (misalign)
author
Tobias Platen
<tplaten@posteo.de>
Mon, 13 Dec 2021 13:40:39 +0000
(14:40 +0100)
committer
Tobias Platen
<tplaten@posteo.de>
Mon, 13 Dec 2021 13:40:39 +0000
(14:40 +0100)
src/soc/experiment/test/test_ldst_pi_misalign.py
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diff --git
a/src/soc/experiment/test/test_ldst_pi_misalign.py
b/src/soc/experiment/test/test_ldst_pi_misalign.py
index 96479bdc0ebe354e6c2e2b2d3133f393c793fc3c..c3faa85e0c4091d103f8074e3318f55b6bdf0c5a 100644
(file)
--- a/
src/soc/experiment/test/test_ldst_pi_misalign.py
+++ b/
src/soc/experiment/test/test_ldst_pi_misalign.py
@@
-27,6
+27,8
@@
from nmigen.compat.sim import run_simulation
from openpower.test.wb_get import wb_get
from openpower.test import wb_get as wbget
from openpower.test.wb_get import wb_get
from openpower.test import wb_get as wbget
+msr_default = MSRSpec(pr=1, dr=0, sf=1) # 64 bit by default
+
wbget.stop = False
wbget.stop = False
@@
-76,21
+78,21
@@
def ldst_sim_misalign(dut):
# load 8 bytes at aligned address
align_addr = 0x1000
data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
# load 8 bytes at aligned address
align_addr = 0x1000
data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
- align_addr, 8, msr
_pr=1
)
+ align_addr, 8, msr
=msr_default
)
print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
assert data == 0xdeadbeef01234567
# load 4 bytes at aligned address
align_addr = 0x1004
data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
assert data == 0xdeadbeef01234567
# load 4 bytes at aligned address
align_addr = 0x1004
data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
- align_addr, 4, msr
_pr=1
)
+ align_addr, 4, msr
=msr_default
)
print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
assert data == 0xdeadbeef
# load 8 bytes at *mis*-aligned address
misalign_addr = 0x1004
data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
assert data == 0xdeadbeef
# load 8 bytes at *mis*-aligned address
misalign_addr = 0x1004
data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
- misalign_addr, 8, msr
_pr=1
)
+ misalign_addr, 8, msr
=msr_default
)
print ("ldst_sim_misalign", data, exctype, exc)
yield
dar = yield dut.submodules.ldst.dar
print ("ldst_sim_misalign", data, exctype, exc)
yield
dar = yield dut.submodules.ldst.dar