+class IntFPIssueUnit(Elaboratable):
+ def __init__(self, wid, n_int_insns, n_fp_insns):
+ self.i = IssueUnit(wid, n_int_insns)
+ self.f = IssueUnit(wid, n_fp_insns)
+ self.issue_o = Signal(reset_less=True)
+
+ # some renames
+ self.int_write_pending_i = self.i.g_wr_pend_i
+ self.fp_write_pending_i = self.f.g_wr_pend_i
+ self.int_write_pending_i.name = 'int_write_pending_i'
+ self.fp_write_pending_i.name = 'fp_write_pending_i'
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.intissue = self.i
+ m.submodules.fpissue = self.f
+
+ m.d.comb += self.issue_o.eq(self.i.g_issue_o | self.f.g_issue_o)
+
+ return m
+
+ def ports(self):
+ yield self.issue_o
+ yield from self.i
+ yield from self.f
+
+