used for 2nd write (currently LD/ST update only)
'sv_in2': SVEXTRA,
'sv_in3': SVEXTRA,
'sv_out': SVEXTRA,
'sv_in2': SVEXTRA,
'sv_in3': SVEXTRA,
'sv_out': SVEXTRA,
'sv_cr_in': SVEXTRA,
'sv_cr_out': SVEXTRA,
'ldst_len': LdstLen,
'sv_cr_in': SVEXTRA,
'sv_cr_out': SVEXTRA,
'ldst_len': LdstLen,
'sv_in2': 'sv_in2',
'sv_in3': 'sv_in3',
'sv_out': 'sv_out',
'sv_in2': 'sv_in2',
'sv_in3': 'sv_in3',
'sv_out': 'sv_out',
'sv_cr_in': 'sv_cr_in',
'sv_cr_out': 'sv_cr_out',
'SV_Etype': 'SV_Etype',
'sv_cr_in': 'sv_cr_in',
'sv_cr_out': 'sv_cr_out',
'SV_Etype': 'SV_Etype',
subset.add("sv_in2")
subset.add("sv_in3")
subset.add("sv_out")
subset.add("sv_in2")
subset.add("sv_in3")
subset.add("sv_out")
subset.add("sv_cr_in")
subset.add("sv_cr_out")
subset.add("SV_Etype")
subset.add("sv_cr_in")
subset.add("sv_cr_out")
subset.add("SV_Etype")
comb += in2_svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (in2_sel)
comb += in3_svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (in3_sel)
comb += o_svdec.idx.eq(op.sv_out) # SVP64 output (out_sel)
comb += in2_svdec.idx.eq(op.sv_in2) # SVP64 reg #2 (in2_sel)
comb += in3_svdec.idx.eq(op.sv_in3) # SVP64 reg #3 (in3_sel)
comb += o_svdec.idx.eq(op.sv_out) # SVP64 output (out_sel)
+ comb += o2_svdec.idx.eq(op.sv_out2) # SVP64 output (implicit)
# XXX TODO - work out where this should come from. the problem is
# that LD-with-update is implied (computed from "is instruction in
# "update mode" rather than specified cleanly as its own CSV column
# XXX TODO - work out where this should come from. the problem is
# that LD-with-update is implied (computed from "is instruction in
# "update mode" rather than specified cleanly as its own CSV column
- #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
# output reg-is-vectorised (and when no in/out is vectorised)
comb += self.in1_isvec.eq(in1_svdec.isvec)
# output reg-is-vectorised (and when no in/out is vectorised)
comb += self.in1_isvec.eq(in1_svdec.isvec)