+ with open("test_compunit1.il", "w") as f:
+ f.write(vl)
+
+ run_simulation(m, scoreboard_sim(dut), vcd_name='test_compunit1.vcd')
+
+
+def test_compunit_regspec1():
+ from alu_hier import ALU
+ from soc.fu.alu.alu_input_record import CompALUOpSubset
+
+ inspec = [('INT', 'a', '0:15'),
+ ('INT', 'b', '0:15')]
+ outspec = [('INT', 'o', '0:15'),
+ ]
+
+ regspec = (inspec, outspec)
+
+ m = Module()
+ alu = ALU(16)
+ dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
+ m.submodules.cu = dut
+
+ vl = rtlil.convert(dut, ports=dut.ports())
+ with open("test_compunit_regspec1.il", "w") as f: