+class DivPipeCoreConfig:
+ """ Configuration for core of the div/rem/sqrt/rsqrt pipeline.
+
+ :attribute bit_width: base bit-width.
+ :attribute fract_width: base fract-width. Specifies location of base-2
+ radix point.
+ :attribute log2_radix: number of bits of ``quotient_root`` that should be
+ computed per pipeline stage.
+ """
+
+ def __init__(self, bit_width, fract_width, log2_radix, supported=None):
+ """ Create a ``DivPipeCoreConfig`` instance. """
+ self.bit_width = bit_width
+ self.fract_width = fract_width
+ self.log2_radix = log2_radix
+ if supported is None:
+ supported = [DP.SqrtRem, DP.UDivRem, DP.RSqrtRem]
+ self.supported = supported
+ print(f"{self}: n_stages={self.n_stages}")
+
+ def __repr__(self):
+ """ Get repr. """
+ return f"DivPipeCoreConfig({self.bit_width}, " \
+ + f"{self.fract_width}, {self.log2_radix})"
+
+ @property
+ def n_stages(self):
+ """ Get the number of ``DivPipeCoreCalculateStage`` needed. """
+ return (self.bit_width + self.log2_radix - 1) // self.log2_radix
+
+