whoops naming pads different from nets is important

diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index 54a8a32e08e66e64a83da1025380c0b83f235251..23e40d02ef14827b6188dea9a0aef765db6a4149 100644 (file)
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -57,13 +57,13 @@ def scriptMain ( **kw ):
          , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'     )
          , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
          , (IoPin.NORTH, None, 'p_pll_test'    , 'pll_test' , 'pll_test'     )
-         , (IoPin.NORTH, None, 'a0'    , 'a0' , 'a0'     )
-         , (IoPin.NORTH, None, 'a1'    , 'a1' , 'a1'     )
+         , (IoPin.NORTH, None, 'p_pll_a0'    , 'a0' , 'a0'     )
+         , (IoPin.NORTH, None, 'p_pll_a1'    , 'a1' , 'a1'     )
          , (IoPin.NORTH, None, 'p_sys_rst'  , 'rst'    , 'rst'      )
          , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'     )
          , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'     )
          , (IoPin.WEST , None, 'power_1'    , 'vdd'    )
-         , (IoPin.WEST , None, 'coresync_clk', 'coresync_clk', 'coresync_clk' )
+         , (IoPin.WEST , None, 'p_coresync_clk', 'coresync_clk', 'coresync_clk' )
          #, (IoPin.WEST , None, 'coresync_rst', 'coresync_rst', 'coresync_rst' )
          , (IoPin.WEST , None, 'p_f1'       , 'f(1)'   , 'f(1)'     )
          , (IoPin.WEST , None, 'p_f0'       , 'f(0)'   , 'f(0)'     )