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reduce am0/bm0 by 2 bits in DIV
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 23 Jul 2019 21:44:25 +0000
(22:44 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 23 Jul 2019 21:44:25 +0000
(22:44 +0100)
src/ieee754/fpdiv/div0.py
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diff --git
a/src/ieee754/fpdiv/div0.py
b/src/ieee754/fpdiv/div0.py
index 3c6c0b1f45b4306383573f76d6e8ac2fcd3d6bda..91baea6b575ad8b44ffbc88db6cf755d59a5e23f 100644
(file)
--- a/
src/ieee754/fpdiv/div0.py
+++ b/
src/ieee754/fpdiv/div0.py
@@
-83,8
+83,8
@@
class FPDivStage0Mod(Elaboratable):
# DIV
with m.If(self.i.ctx.op == 0):
- am0 = Signal(len(self.i.a.m)+
3
, reset_less=True)
- bm0 = Signal(len(self.i.b.m)+
3
, reset_less=True)
+ am0 = Signal(len(self.i.a.m)+
1
, reset_less=True)
+ bm0 = Signal(len(self.i.b.m)+
1
, reset_less=True)
m.d.comb += [
am0.eq(Cat(self.i.a.m, 0)),
bm0.eq(Cat(self.i.b.m, 0)),