dependency cells enable on q not qn

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 45325398425bcfe5eb8d638abd1433b6f888dab7..c2ec3d89732be9f906daf8cebe1b1d130d8ee24b 100644 (file)
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -75,7 +75,7 @@ class Scoreboard(Elaboratable):
         intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
         m.submodules.intfudeps = intfudeps
         # Integer FU-Reg Dep Matrix
-        intregdeps = FURegDepMatrix(self.n_regs, n_int_fus)
+        intregdeps = FURegDepMatrix(n_int_fus, self.n_regs)
         m.submodules.intregdeps = intregdeps
 
         # Integer Priority Picker 1: Adder + Subtractor
@@ -144,11 +144,11 @@ class Scoreboard(Elaboratable):
         # Group Picker... done manually for now.  TODO: cat array of pick sigs
         go_rd_i = intfudeps.go_rd_i
         go_wr_i = intfudeps.go_wr_i
-        m.d.comb += go_rd_i[0].eq(intpick1.go_rd_o[0]) # add rd
-        m.d.comb += go_wr_i[0].eq(intpick1.go_wr_o[0]) # add wr
+        m.d.sync += go_rd_i[0].eq(intpick1.go_rd_o[0]) # add rd
+        m.d.sync += go_wr_i[0].eq(intpick1.go_wr_o[0]) # add wr
 
-        m.d.comb += go_rd_i[1].eq(intpick1.go_rd_o[1]) # sub rd
-        m.d.comb += go_wr_i[1].eq(intpick1.go_wr_o[1]) # sub wr
+        m.d.sync += go_rd_i[1].eq(intpick1.go_rd_o[1]) # sub rd
+        m.d.sync += go_wr_i[1].eq(intpick1.go_wr_o[1]) # sub wr
 
         m.d.comb += intfudeps.issue_i.eq(fn_issue_o)
 
@@ -190,10 +190,8 @@ class Scoreboard(Elaboratable):
 
         # connect ALUs
         for i, alu in enumerate(int_alus):
-            m.d.comb += alu.go_rd_i.eq(intpick1.go_rd_o[i])
-            m.d.comb += alu.go_wr_i.eq(intpick1.go_wr_o[i])
-            #m.d.comb += alu.issue_i.eq(fn_issue_l[i])
-            #m.d.comb += fn_busy_l[i].eq(alu.busy_o)  # XXX ignore, use fnissue
+            m.d.comb += alu.go_rd_i.eq(go_rd_i[i])
+            m.d.comb += alu.go_wr_i.eq(go_wr_i[i])
             m.d.comb += alu.src1_i.eq(int_src1.data_o)
             m.d.comb += alu.src2_i.eq(int_src2.data_o)
 
@@ -300,7 +298,7 @@ def scoreboard_sim(dut, alusim):
 
         yield from alusim.check(dut)
 
-    for i in range(100):
+    for i in range(4):
         src1 = randint(1, dut.n_regs-1)
         src2 = randint(1, dut.n_regs-1)
         while True:

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 5b7baea8c66f94af39b2c868c1daa5e3d1a6a05f..cb560c1a29f2c802c22affdf72950d9a99c18784 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -29,9 +29,9 @@ class DependenceCell(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.dest_l = dest_l = SRLatch()
-        m.submodules.src1_l = src1_l = SRLatch()
-        m.submodules.src2_l = src2_l = SRLatch()
+        m.submodules.dest_l = dest_l = SRLatch() # clock-sync'd
+        m.submodules.src1_l = src1_l = SRLatch() # clock-sync'd
+        m.submodules.src2_l = src2_l = SRLatch() # clock-sync'd
 
         # destination latch: reset on go_wr HI, set on dest and issue
         m.d.comb += dest_l.s.eq(self.issue_i & self.dest_i)
@@ -42,18 +42,18 @@ class DependenceCell(Elaboratable):
         m.d.comb += src1_l.r.eq(self.go_rd_i)
 
         # src2 latch: reset on go_rd HI, set on op2_i and issue
-        m.d.comb += src2_l.s.eq(self.issue_i & self.src2_i)
-        m.d.comb += src2_l.r.eq(self.go_rd_i)
+        m.d.sync += src2_l.s.eq(self.issue_i & self.src2_i)
+        m.d.sync += src2_l.r.eq(self.go_rd_i)
 
         # FU "Forward Progress" (read out horizontally)
-        m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i)
-        m.d.comb += self.src1_fwd_o.eq(src1_l.qn & self.src1_i)
-        m.d.comb += self.src2_fwd_o.eq(src2_l.qn & self.src2_i)
+        m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.dest_i)
+        m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.src1_i)
+        m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.src2_i)
 
         # Register File Select (read out vertically)
-        m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_wr_i)
-        m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_rd_i)
-        m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_rd_i)
+        m.d.comb += self.dest_rsel_o.eq(dest_l.q & self.go_wr_i)
+        m.d.comb += self.src1_rsel_o.eq(src1_l.q & self.go_rd_i)
+        m.d.comb += self.src2_rsel_o.eq(src2_l.q & self.go_rd_i)
 
         return m
 

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index 250ba85b91cc74f598328f7b56e324aabc5cd1e1..9f4bceb48d0f5c4dc706eb6af14744022dbea992 100644 (file)
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -22,8 +22,8 @@ class FUDependenceCell(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.rd_l = rd_l = SRLatch()
-        m.submodules.wr_l = wr_l = SRLatch()
+        m.submodules.rd_l = rd_l = SRLatch() # clock-sync'd
+        m.submodules.wr_l = wr_l = SRLatch() # clock-sync'd
 
         # write latch: reset on go_wr HI, set on write pending and issue
         m.d.comb += wr_l.s.eq(self.issue_i & self.wr_pend_i)
@@ -34,8 +34,8 @@ class FUDependenceCell(Elaboratable):
         m.d.comb += rd_l.r.eq(self.go_rd_i)
 
         # Read/Write Pending Latches (read out horizontally)
-        m.d.comb += self.wr_pend_o.eq(wr_l.qn)
-        m.d.comb += self.rd_pend_o.eq(rd_l.qn)
+        m.d.comb += self.wr_pend_o.eq(wr_l.q)
+        m.d.comb += self.rd_pend_o.eq(rd_l.q)
 
         return m