idea: invert pos/neg test in output stage, uses an XOR instead of QTY 2 64-bit

MUXes and a mess/morass of code

diff --git a/libreriscv b/libreriscv
index ad0436eed1fcf36e0f1acfde5de71ad2e4b56145..eda9879fef1cddcd9fb41fca982a6b86e471905b 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit ad0436eed1fcf36e0f1acfde5de71ad2e4b56145
+Subproject commit eda9879fef1cddcd9fb41fca982a6b86e471905b

diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py
index f5a50160485615fc8ef2d900382541db07254001..5de9bbd0e50f99b761acbf3f799e7d5a01f49608 100644 (file)
--- a/src/soc/alu/output_stage.py
+++ b/src/soc/alu/output_stage.py
@@ -33,8 +33,12 @@ class ALUOutputStage(PipeModBase):
         is_zero = Signal(reset_less=True)
         is_positive = Signal(reset_less=True)
         is_negative = Signal(reset_less=True)
+        msb_test = Signal(reset_less=True) # set equal to MSB, invert if OP=CMP
         so = Signal(reset_less=True)
 
+        # TODO: if o[63] is XORed with "operand == OP_CMP"
+        # that can be used as a test
+        # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
         comb += is_zero.eq(o == 0)
         comb += is_positive.eq(~is_zero & ~o[63])
         comb += is_negative.eq(~is_zero & o[63])