`ifdef AXIEXP
import axiexpansion ::*;
`endif
- `ifdef QSPI
- import qspi :: *;
- `endif
/*=====================================*/
/*===== interface declaration =====*/
Ifc_AXI4Lite_AXI4_Bridge
bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
- mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
+ mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
/*======= Slave connections to AXI4Lite fabric =========*/
{6}
`ifdef CLINT
Copyright (c) 2013, IIT Madras
All rights reserved.
-Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
-* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
-* Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+* Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+* Neither the name of IIT Madras nor the names of its contributors
+ may be used to endorse or promote products derived from this software
+ without specific prior written permission.
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-------------------------------------------------------------------
*/
package Soc;
- /*====== Package imports === */
- import FIFO::*;
- import FIFOF::*;
- import SpecialFIFOs::*;
- import GetPut::*;
- import ClientServer::*;
- import Vector::*;
- import Connectable::*;
- import Clocks::*;
- /*========================== */
- /*=== Project imports === */
- import ConcatReg::*;
- import AXI4_Types::*;
- import AXI4_Fabric::*;
- import defined_types::*;
- import MemoryMap :: *;
- import slow_peripherals::*;
- `include "defines.bsv"
- `include "instance_defines.bsv"
+ /*====== Package imports === */
+ import FIFO::*;
+ import FIFOF::*;
+ import SpecialFIFOs::*;
+ import GetPut::*;
+ import ClientServer::*;
+ import Vector::*;
+ import Connectable::*;
+ import Clocks::*;
+ /*========================== */
+ /*=== Project imports === */
+ import ConcatReg::*;
+ import AXI4_Types::*;
+ import AXI4_Fabric::*;
+ import defined_types::*;
+ import MemoryMap :: *;
+ import slow_peripherals::*;
+ `include "defines.bsv"
+ `include "instance_defines.bsv"
{8}
/*====== AXI4 slave declarations =======*/
{3}
{4}
- `ifdef DMA
- import DMA :: *;
- `endif
- `ifdef BOOTROM
- import BootRom ::*;
- `endif
- `ifdef SDRAM
- import sdr_top :: *;
+ `ifdef DMA
+ import DMA :: *;
+ `endif
+ `ifdef BOOTROM
+ import BootRom ::*;
+ `endif
+ `ifdef SDRAM
+ import sdr_top :: *;
`endif
- `ifdef BRAM
- import Memory_AXI4 ::*;
- `endif
- `ifdef TCMemory
- import TCM::*;
- `endif
- `ifdef Debug
- import jtagdtm::*;
- import DebugModule::*;
- `else
- import core::*;
- `endif
+ `ifdef BRAM
+ import Memory_AXI4 ::*;
+ `endif
+ `ifdef TCMemory
+ import TCM::*;
+ `endif
+ `ifdef Debug
+ import jtagdtm::*;
+ import DebugModule::*;
+ `else
+ import core::*;
+ `endif
`ifdef VME
- import vme_top ::*;
+ import vme_top ::*;
`endif
`ifdef VME
- import vme_master::*;
+ import vme_master::*;
`endif
`ifdef FlexBus
import FlexBus_Types::*;
`endif
{0}
- /*========================= */
- interface Ifc_Soc;
- interface SP_ios slow_ios;
- (*always_ready,always_enabled*)
- method Action boot_sequence(Bit#(1) bootseq);
-
- `ifdef SDRAM
- (*always_ready*) interface Ifc_sdram_out sdram_out;
- `endif
+ /*========================= */
+ interface Ifc_Soc;
+ interface SP_ios slow_ios;
+ (*always_ready,always_enabled*)
+ method Action boot_sequence(Bit#(1) bootseq);
+
+ `ifdef SDRAM
+ (*always_ready*) interface Ifc_sdram_out sdram_out;
+ `endif
`ifdef DDR
(*prefix="M_AXI"*) interface
AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
`endif
- `ifdef HYPER
- (*always_ready,always_enabled*)
- interface Ifc_flash ifc_flash;
- `endif
- /*=============================================== */
- `ifdef VME
- interface Vme_out proc_ifc;
- interface Data_bus_inf proc_dbus;
- `endif
+ `ifdef HYPER
+ (*always_ready,always_enabled*)
+ interface Ifc_flash ifc_flash;
+ `endif
+ /*=============================================== */
+ `ifdef VME
+ interface Vme_out proc_ifc;
+ interface Data_bus_inf proc_dbus;
+ `endif
`ifdef FlexBus
interface FlexBus_Master_IFC flexbus_out;
`endif
{1}
- endinterface
- (*synthesize*)
- module mkSoc #(Bit#(`VADDR) reset_vector,
+ endinterface
+ (*synthesize*)
+ module mkSoc #(Bit#(`VADDR) reset_vector,
Clock slow_clock, Reset slow_reset, Clock uart_clock,
Reset uart_reset, Clock clk0, Clock tck, Reset trst
`ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
- Clock core_clock <-exposeCurrentClock; // slow peripheral clock
- Reset core_reset <-exposeCurrentReset; // slow peripheral reset
+ Clock core_clock <-exposeCurrentClock; // slow peripheral clock
+ Reset core_reset <-exposeCurrentReset; // slow peripheral reset
{2}
`ifdef Debug
- Ifc_DebugModule core<-mkDebugModule(reset_vector);
- `else
- Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
- `endif
- `ifdef BOOTROM
- BootRom_IFC bootrom <-mkBootRom;
- `endif
- `ifdef SDRAM
- Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
- `endif
+ Ifc_DebugModule core<-mkDebugModule(reset_vector);
+ `else
+ Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
+ `endif
+ `ifdef BOOTROM
+ BootRom_IFC bootrom <-mkBootRom;
+ `endif
+ `ifdef SDRAM
+ Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
+ `endif
`ifdef BRAM
- Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
+ Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
- `endif
- `ifdef TCMemory
- Ifc_TCM tcm <- mkTCM;
- `endif
- `ifdef DMA
- DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
- `endif
- `ifdef VME
- Ifc_vme_top vme <-mkvme_top();
- `endif
+ `endif
+ `ifdef TCMemory
+ Ifc_TCM tcm <- mkTCM;
+ `endif
+ `ifdef DMA
+ DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
+ `endif
+ `ifdef VME
+ Ifc_vme_top vme <-mkvme_top();
+ `endif
`ifdef FlexBus
AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
`endif
- Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
+ Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
core_clock, core_reset, uart_clock,
uart_reset, clocked_by slow_clock , reset_by slow_reset
`ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
- // Fabric
- AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
- fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
+ // Fabric
+ AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
+ fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
- // Connect traffic generators to fabric
- mkConnection (core.dmem_master,fabric.v_from_masters
+ // Connect traffic generators to fabric
+ mkConnection (core.dmem_master,fabric.v_from_masters
[fromInteger(valueOf(Dmem_master_num))]);
- mkConnection (core.imem_master, fabric.v_from_masters
+ mkConnection (core.imem_master, fabric.v_from_masters
[fromInteger(valueOf(Imem_master_num))]);
- `ifdef Debug
- mkConnection (core.debug_master, fabric.v_from_masters
+ `ifdef Debug
+ mkConnection (core.debug_master, fabric.v_from_masters
[fromInteger(valueOf(Debug_master_num))]);
- `endif
- `ifdef DMA
+ `endif
+ `ifdef DMA
mkConnection (dma.mmu, fabric.v_from_masters
[fromInteger(valueOf(DMA_master_num))]);
- `endif
+ `endif
- // Connect fabric to memory slaves
- `ifdef Debug
- mkConnection (fabric.v_to_slaves
+ // Connect fabric to memory slaves
+ `ifdef Debug
+ mkConnection (fabric.v_to_slaves
[fromInteger(valueOf(Debug_slave_num))],
core.debug_slave);
- `endif
- `ifdef SDRAM
- mkConnection (fabric.v_to_slaves
+ `endif
+ `ifdef SDRAM
+ mkConnection (fabric.v_to_slaves
[fromInteger(valueOf(Sdram_slave_num))],
sdram.axi4_slave_sdram); //
- mkConnection (fabric.v_to_slaves
+ mkConnection (fabric.v_to_slaves
[fromInteger(valueOf(Sdram_cfg_slave_num))],
sdram.axi4_slave_cntrl_reg); //
`endif
`ifdef BRAM
- mkConnection(fabric.v_to_slaves
+ mkConnection(fabric.v_to_slaves
[fromInteger(valueOf(Sdram_slave_num))],
main_memory.axi_slave);
- `endif
- `ifdef BOOTROM
- mkConnection (fabric.v_to_slaves
+ `endif
+ `ifdef BOOTROM
+ mkConnection (fabric.v_to_slaves
[fromInteger(valueOf(BootRom_slave_num))],
bootrom.axi_slave);
- `endif
- `ifdef DMA
- mkConnection (fabric.v_to_slaves
+ `endif
+ `ifdef DMA
+ mkConnection (fabric.v_to_slaves
[fromInteger(valueOf(Dma_slave_num))],
dma.cfg); //DMA slave
- `endif
- `ifdef TCMemory
- mkConnection (fabric.v_to_slaves
+ `endif
+ `ifdef TCMemory
+ mkConnection (fabric.v_to_slaves
[fromInteger(valueOf(TCM_slave_num))],
tcm.axi_slave);
- `endif
- mkConnection(fabric.v_to_slaves
+ `endif
+ mkConnection(fabric.v_to_slaves
[fromInteger(valueOf(SlowPeripheral_slave_num))],
slow_peripherals.axi_slave);
- `ifdef VME
- mkConnection (fabric.v_to_slaves
+ `ifdef VME
+ mkConnection (fabric.v_to_slaves
[fromInteger(valueOf(VME_slave_num))],
vme.slave_axi_vme);
- `endif
- `ifdef FlexBus
- mkConnection (fabric.v_to_slaves
+ `endif
+ `ifdef FlexBus
+ mkConnection (fabric.v_to_slaves
[fromInteger(valueOf(FlexBus_slave_num))],
flexbus.axi_side);
- `endif
+ `endif
// fabric connections
{5}
- `ifdef DMA
- // rule to connect all interrupt lines to the DMA
- // All the interrupt lines to DMA are active
- // HIGH. For peripherals that are not connected,
- // or those which do not
- // generate an interrupt (like TCM), drive a constant 1
+ `ifdef DMA
+ // rule to connect all interrupt lines to the DMA
+ // All the interrupt lines to DMA are active
+ // HIGH. For peripherals that are not connected,
+ // or those which do not
+ // generate an interrupt (like TCM), drive a constant 1
// on the corresponding interrupt line.
{7}
- `endif
+ `endif
- /*==== Synchornization between the JTAG and the Debug Module ===== */
- `ifdef Debug
- SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
+ /*==== Synchornization between the JTAG and the Debug Module ===== */
+ `ifdef Debug
+ SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
mkSyncFIFOToCC(1,tck,trst);
- SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
+ SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
mkSyncFIFOFromCC(1,tck);
- rule connect_tap_request_to_syncfifo;
- let x<-tap.request_to_dm;
- sync_request_to_dm.enq(x);
- endrule
- rule read_synced_request_to_dm;
- sync_request_to_dm.deq;
- core.request_from_dtm(sync_request_to_dm.first);
- endrule
+ rule connect_tap_request_to_syncfifo;
+ let x<-tap.request_to_dm;
+ sync_request_to_dm.enq(x);
+ endrule
+ rule read_synced_request_to_dm;
+ sync_request_to_dm.deq;
+ core.request_from_dtm(sync_request_to_dm.first);
+ endrule
- rule connect_debug_response_to_syncfifo;
- let x<-core.response_to_dtm;
- sync_response_from_dm.enq(x);
- endrule
- rule read_synced_response_from_dm;
- sync_response_from_dm.deq;
- tap.response_from_dm(sync_response_from_dm.first);
- endrule
- `endif
- /*============================================================ */
-
+ rule connect_debug_response_to_syncfifo;
+ let x<-core.response_to_dtm;
+ sync_response_from_dm.enq(x);
+ endrule
+ rule read_synced_response_from_dm;
+ sync_response_from_dm.deq;
+ tap.response_from_dm(sync_response_from_dm.first);
+ endrule
+ `endif
+ /*============================================================ */
+
`ifdef FlexBus
//rule drive_flexbus_inputs;
//flexbus.flexbus_side.m_TAn(1'b1);
//endrule
`endif
- `ifdef CLINT
- SyncBitIfc#(Bit#(1)) clint_mtip_int <-
+ `ifdef CLINT
+ SyncBitIfc#(Bit#(1)) clint_mtip_int <-
mkSyncBitToCC(slow_clock,slow_reset);
- SyncBitIfc#(Bit#(1)) clint_msip_int <-
+ SyncBitIfc#(Bit#(1)) clint_msip_int <-
mkSyncBitToCC(slow_clock,slow_reset);
- Reg#(Bit#(`Reg_width)) clint_mtime_value <-
+ Reg#(Bit#(`Reg_width)) clint_mtime_value <-
mkSyncRegToCC(0,slow_clock,slow_reset);
- rule synchronize_clint_data;
- clint_mtip_int.send(slow_peripherals.mtip_int);
- clint_msip_int.send(slow_peripherals.msip_int);
- clint_mtime_value<=slow_peripherals.mtime;
- endrule
- rule connect_msip_mtip_from_clint;
- core.clint_msip(clint_msip_int.read);
- core.clint_mtip(clint_mtip_int.read);
+ rule synchronize_clint_data;
+ clint_mtip_int.send(slow_peripherals.mtip_int);
+ clint_msip_int.send(slow_peripherals.msip_int);
+ clint_mtime_value<=slow_peripherals.mtime;
+ endrule
+ rule connect_msip_mtip_from_clint;
+ core.clint_msip(clint_msip_int.read);
+ core.clint_mtip(clint_mtip_int.read);
core.clint_mtime(clint_mtime_value);
- endrule
- `endif
- `ifdef PLIC
- Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
+ endrule
+ `endif
+ `ifdef PLIC
+ Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
mkSyncRegToCC(tuple2(False,False),
slow_clock,slow_reset);
- rule synchronize_interrupts;
- let note <- slow_peripherals.intrpt_note;
- plic_interrupt_note<=note;
- endrule
- rule rl_send_external_interrupt_to_csr;
- core.set_external_interrupt(plic_interrupt_note);
- endrule
- `endif
+ rule synchronize_interrupts;
+ let note <- slow_peripherals.intrpt_note;
+ plic_interrupt_note<=note;
+ endrule
+ rule rl_send_external_interrupt_to_csr;
+ core.set_external_interrupt(plic_interrupt_note);
+ endrule
+ `endif
- `ifdef VME
- interface proc_ifc = vme.proc_ifc;
- interface proc_dbus = vme.proc_dbus;
- `endif
- `ifdef FlexBus
+ `ifdef VME
+ interface proc_ifc = vme.proc_ifc;
+ interface proc_dbus = vme.proc_dbus;
+ `endif
+ `ifdef FlexBus
interface flexbus_out = flexbus.flexbus_side;
- `endif
- method Action boot_sequence(Bit#(1) bootseq) =
+ `endif
+ method Action boot_sequence(Bit#(1) bootseq) =
core.boot_sequence(bootseq);
- `ifdef SDRAM
- interface sdram_out=sdram.ifc_sdram_out;
- `endif
- `ifdef DDR
- interface master=fabric.v_to_slaves
- [fromInteger(valueOf(Sdram_slave_num))];
- `endif
- interface slow_ios=slow_peripherals.slow_ios;
+ `ifdef SDRAM
+ interface sdram_out=sdram.ifc_sdram_out;
+ `endif
+ `ifdef DDR
+ interface master=fabric.v_to_slaves
+ [fromInteger(valueOf(Sdram_slave_num))];
+ `endif
+ interface slow_ios=slow_peripherals.slow_ios;
{6}
- endmodule
+ endmodule
endpackage
bname = self.axibase(name, ifacenum)
bend = self.axiend(name, ifacenum)
name = self.axi_slave_name(name, ifacenum)
- return """\
- if(addr>=`{0} && addr<=`{1})
- return tuple2(True,fromInteger(valueOf({2})));
- else""".format(bname, bend, name)
+ template = """\
+if(addr>=`{0} && addr<=`{1})
+ return tuple2(True,fromInteger(valueOf({2})));
+else"""
+ return template.format(bname, bend, name)
def mk_pincon(self, name, count):
# TODO: really should be using bsv.interface_decl.Interfaces
pname = p['name']
#n = "{0}{1}".format(self.name, self.mksuffix(name, count))
n = name # "{0}{1}".format(self.name, self.mksuffix(name, count))
- ret.append(" //%s %s" % (n, str(p)))
+ ret.append("//%s %s" % (n, str(p)))
sname = self.peripheral.iname().format(count)
sname = "{0}.{1}".format(sname, pname)
ps = "pinmux.peripheral_side.%s" % sname
n_ = '{0}.{1}'.format(n_, fname)
n_ = self.ifname_tweak(pname, 'in', n_)
ret.append("mkConnection({1}, {0});".format(ps_, n_))
- return '\n'.join(li(ret, 6))
+ return '\n'.join(ret)
def mk_cellconn(self, *args):
return ''
print "PBase __mk_connection", self.name, aname
if not con:
return ''
- return li(txt.format(con, aname, fabricname), 8)
+ return txt.format(con, aname, fabricname)
def __mk_master_connection(self, con, aname):
txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
print "PBase __mk_connection", self.name, aname
if not con:
return ''
- return li(txt.format(con, aname), 8)
+ return txt.format(con, aname)
def mk_connection(self, count, fabricname, typ, name=None):
if name is None:
plic = mkplic_rule.format(name, plic_obj, irq_offs)
res.append(plic)
irq_offs += 1 # increment to next irq
- return ('\n'.join(li(res, 5)), irq_offs)
+ return ('\n'.join(res), irq_offs)
def mk_ext_ifacedef(self, iname, inum):
return ''
sname = pname
else:
sname = self.peripheral.iname().format(count)
- template = " interface {0}{3} = {2}{1};"
+ template = "interface {0}{3} = {2}{1};"
return template.format(pname, sname, prefix, suffix)
def extifinstance2(self, name, count):
"""
pinmux_cellrule = """\
- rule connect_select_lines_pinmux;
+rule connect_select_lines_pinmux;
{0}
- endrule
+endrule
"""
for (name, count) in self.ifacecount:
#print "slowimport", name, self.data[name].slowimport
ret.append(self.data[name].slowimport())
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 4))
def extfastifinstance(self, *args):
ret = []
if self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].extfastifinstance(name, i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def extifinstance2(self, *args):
ret = []
for i in range(count):
iname = self.data[name].iname().format(i)
ret.append(self.data[name].extifinstance2(name, i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def extifinstance(self, *args):
ret = []
if not self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].extifinstance(name, i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def extifdecl(self, *args):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
ret.append(self.data[name].slowifdeclmux(name, i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def fastifdecl(self, *args):
ret = []
if self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].fastifdecl(name, i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 4))
def slowifdecl(self, *args):
ret = []
if self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].axi_addr_map(i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mkfast_peripheral(self, *args):
ret = []
print name, count, x
suffix = self.data[name].mksuffix(name, i)
ret.append(x.format(suffix))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mkslow_peripheral(self, *args):
ret = []
print name, count, x
suffix = self.data[name].mksuffix(name, i)
ret.append(x.format(suffix))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mk_fast_connection(self, *args):
ret = []
print "txt", txt
print self.data[name].mk_connection
ret.append(txt)
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 4))
def mk_connection(self, *args):
ret = []
print "txt", txt
print self.data[name].mk_connection
ret.append(txt)
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mk_cellconn(self):
ret = []
continue
(txt, cellcount) = res
ret.append(txt)
- ret = '\n'.join(list(filter(None, ret)))
- return pinmux_cellrule.format(ret)
+ ret = li('\n'.join(list(filter(None, ret))), 4)
+ return li(pinmux_cellrule.format(ret), 4)
def mk_pincon(self):
ret = []
continue
txt = self.data[name].mk_pincon(name, i)
ret.append(txt)
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 4))
def mk_dma_irq(self):
ret = []
continue
txt = self.data[name].mk_ext_ifacedef(name, i)
ret.append(txt)
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mk_plic(self):
ret = []
(txt, irq_offs) = res
ret.append(txt)
self.num_slow_irqs = irq_offs
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 4))
def mk_sloirqsdef(self):
return " `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
def slowimport(self):
size = len(self.peripheral.pinspecs)
- return " `define NUM_EINTS %d" % size
+ return "`define NUM_EINTS %d" % size
def mkslow_peripheral(self, size=0):
size = len(self.peripheral.pinspecs)
- return " Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
+ return "Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
def axi_slave_name(self, name, ifacenum, typ=''):
return ''
ret = [PBase.mk_pincon(self, name, count)]
size = len(self.peripheral.pinspecs)
ret.append(eint_pincon_template.format(size))
- ret.append(" rule con_%s%d_io_in;" % (name, count))
- ret.append(" wr_interrupt <= ({")
+ ret.append("rule con_%s%d_io_in;" % (name, count))
+ ret.append(" wr_interrupt <= ({")
for idx, p in enumerate(self.peripheral.pinspecs):
pname = p['name']
sname = self.peripheral.pname(pname).format(count)
ps = "pinmux.peripheral_side.eint.%s" % sname
comma = '' if idx == size - 1 else ','
ret.append(" {0}{1}".format(ps, comma))
- ret.append(" });")
- ret.append(" endrule")
+ ret.append(" });")
+ ret.append("endrule")
return '\n'.join(ret)
class gpio(PBase):
def slowimport(self):
- return " import pinmux::*;\n" + \
- " import mux::*;\n" + \
- " import gpio::*;\n"
+ return "import pinmux::*;\n" + \
+ "import mux::*;\n" + \
+ "import gpio::*;\n"
def extifinstance2(self, name, count):
template = "interface pad_config{0} = {1}.pad_config;"
def mkslow_peripheral(self, size=0):
print "gpioslow", self.peripheral, dir(self.peripheral)
size = len(self.peripheral.pinspecs)
- return " MUX#(%d) mux{0} <- mkmux();\n" % size + \
- " GPIO#(%d) gpio{0} <- mkgpio();" % size
+ return "MUX#(%d) mux{0} <- mkmux();\n" % size + \
+ "GPIO#(%d) gpio{0} <- mkgpio();" % size
def mk_connection(self, count, fabricname, typ):
print "GPIO mk_conn", self.name, count
def mk_cellconn(self, cellnum, name, count):
ret = []
bank = self.mksuffix(name, count)
- txt = " pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
+ txt = "pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
for p in self.peripheral.pinspecs:
ret.append(txt.format(cellnum, bank, p['name'][1:]))
cellnum += 1
# special-case for gpio in, store in a temporary vector
ret = []
plen = len(self.peripheral.pinspecs)
- template = " mkConnection({0}.{1},\n\t\t\t{2}_{1});"
+ template = "mkConnection({0}.{1},\n\t\t\t{2}_{1});"
ps = "pinmux.peripheral_side.%s" % name
n = "{0}.func.gpio".format(name)
for ptype in ['out', 'out_en', 'in']:
class jtag(PBase):
def slowimport(self):
- return " import jtagtdm::*;\n"
+ return "import jtagtdm::*;\n"
def extfastifinstance(self, name, count):
return self._extifinstance(name, count, "_out", "", True)
-
def fastifdecl(self, name, count):
# YUK!
- return " Ifc_jtagdtm jtag{0}_out;".format(count);
+ return "Ifc_jtagdtm jtag{0}_out;".format(count);
def mkfast_peripheral(self):
return """\
- Ifc_jtagdtm jtag{0} <-mkjtagdtm(clocked_by tck, reset_by trst);
- rule drive_tmp_scan_outs;
- jtag{0}.scan_out_1_i(1'b0);
- jtag{0}.scan_out_2_i(1'b0);
- jtag{0}.scan_out_3_i(1'b0);
- jtag{0}.scan_out_4_i(1'b0);
- jtag{0}.scan_out_5_i(1'b0);
- endrule
+Ifc_jtagdtm jtag{0} <-mkjtagdtm(clocked_by tck, reset_by trst);
+rule drive_tmp_scan_outs;
+ jtag{0}.scan_out_1_i(1'b0);
+ jtag{0}.scan_out_2_i(1'b0);
+ jtag{0}.scan_out_3_i(1'b0);
+ jtag{0}.scan_out_4_i(1'b0);
+ jtag{0}.scan_out_5_i(1'b0);
+endrule
"""
def axi_slave_name(self, name, ifacenum, typ=''):
return ''
assert masteronly, "Only master only %s supported for now" % name
def slowimport(self):
- return " import %(n)s :: *;" % self.ifndict
+ return "import %(n)s :: *;" % self.ifndict
def irq_name(self):
return "%(n)s{0}_isint" % self.ifndict
def slowifdecl(self):
- return " interface %(N)s_out %(n)s{0}_out;\n" + \
- " method Bit#(1) %s;" % self.irq_name
+ return "interface %(N)s_out %(n)s{0}_out;\n" + \
+ "method Bit#(1) %s;" % self.irq_name
def num_axi_regs32(self):
return 13
def mkslow_peripheral(self, size=0):
- return " Ifc_%(n)s %(n)s{0} <- mk%(n)s();" % self.ifndict
+ return "Ifc_%(n)s %(n)s{0} <- mk%(n)s();" % self.ifndict
def _mk_connection(self, name=None, count=0):
return "%(n)s{0}.slave" % self.ifndict
ret = [PBase.mk_pincon(self, name, count)]
# special-case for gpio in, store in a temporary vector
plen = len(self.peripheral.pinspecs)
- template = " mkConnection({0}.{1},\n\t\t\t{2}.{1});"
+ template = "mkConnection({0}.{1},\n\t\t\t{2}.{1});"
sname = self.peripheral.iname().format(count)
name = self.get_iname(count)
ps = "pinmux.peripheral_side.%s" % sname
def mk_ext_ifacedef(self, iname, inum):
name = self.get_iname(inum)
- return " method {0}_isint = {0}.interrupts[5];".format(name)
+ return "method {0}_isint = {0}.interrupts[5];".format(name)
def slowifdeclmux(self, name, count):
sname = self.get_iname(count)
- return " method Bit#(1) %s_isint;" % sname
+ return "method Bit#(1) %s_isint;" % sname
class pwm(PBase):
def slowimport(self):
- return " import pwm::*;"
+ return "import pwm::*;"
def slowifdecl(self):
- return " interface PWMIO pwm{0}_io;"
+ return "interface PWMIO pwm{0}_io;"
def num_axi_regs32(self):
return 4
def mkslow_peripheral(self, size=0):
- return " Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
+ return "Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
def _mk_connection(self, name=None, count=0):
return "pwm{0}.axi4_slave"
class quart(PBase):
def slowimport(self):
- return " import Uart16550 :: *;"
+ return "import Uart16550 :: *;"
def irq_name(self):
return "quart{0}_intr"
def slowifdecl(self):
- return " interface RS232_PHY_Ifc quart{0}_coe;\n" + \
- " method Bit#(1) %s;" % self.irq_name()
+ return "interface RS232_PHY_Ifc quart{0}_coe;\n" + \
+ "method Bit#(1) %s;" % self.irq_name()
def get_clock_reset(self, name, count):
return "slow_clock,slow_reset" # XXX TODO: change to uart_clock/reset
return 8
def mkslow_peripheral(self, size=0):
- return " // XXX XXX TODO: change to uart_clock/reset" + \
- " Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
+ return "// XXX TODO: change to uart_clock/reset" + \
+ "Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
" mkUart16550(clocked_by sp_clock,\n" + \
" reset_by sp_reset, sp_clock, sp_reset);"
def __disabled_mk_pincon(self, name, count):
ret = [PBase.mk_pincon(self, name, count)]
- ret.append(" rule con_%s%d_io_in;" % (name, count))
- ret.append(" {0}{1}.coe_rs232.modem_input(".format(name, count))
+ ret.append("rule con_%s%d_io_in;" % (name, count))
+ ret.append(" {0}{1}.coe_rs232.modem_input(".format(name, count))
for idx, pname in enumerate(['rx', 'cts']):
sname = self.peripheral.pname(pname).format(count)
ps = "pinmux.peripheral_side.%s" % sname
ret.append(" {0},".format(ps))
ret.append(" 1'b1,1'b0,1'b1")
- ret.append(" );")
- ret.append(" endrule")
+ ret.append(" );")
+ ret.append("endrule")
return '\n'.join(ret)
def mk_ext_ifacedef(self, iname, inum):
name = self.get_iname(inum)
- return " method {0}_intr = {0}.irq;".format(name)
+ return "method {0}_intr = {0}.irq;".format(name)
def slowifdeclmux(self, name, count):
sname = self.peripheral.iname().format(count)
- return " method Bit#(1) %s_intr;" % sname
+ return "method Bit#(1) %s_intr;" % sname
uart_plic_template = """\
- // PLIC {0} synchronisation with irq {1}
- SyncBitIfc#(Bit#(1)) {0}_interrupt <-
- mkSyncBitToCC(sp_clock, uart_reset);
- rule plic_synchronize_{0}_interrupt_{1};
- {0}_interrupt.send({0}.irq);
- endrule
+// PLIC {0} synchronisation with irq {1}
+SyncBitIfc#(Bit#(1)) {0}_interrupt <-
+ mkSyncBitToCC(sp_clock, uart_reset);
+rule plic_synchronize_{0}_interrupt_{1};
+ {0}_interrupt.send({0}.irq);
+endrule
"""
class rgbttl(PBase):
def slowimport(self):
- return " import rgbttl_dummy :: *;"
+ return "import rgbttl_dummy :: *;"
def has_axi_master(self):
return True
def mkfast_peripheral(self):
sz = len(self.peripheral.pinspecs) - 4 # subtract CK, DE, HS, VS
- return " Ifc_rgbttl_dummy lcd{0} <- mkrgbttl_dummy();"
+ return "Ifc_rgbttl_dummy lcd{0} <- mkrgbttl_dummy();"
def _mk_connection(self, name=None, count=0):
return "lcd{0}.slave"
# special-case for gpio in, store in a temporary vector
sname = self.peripheral.iname().format(count)
plen = len(self.peripheral.pinspecs)
- template = " mkConnection({0}.{1},\n\t\t\t{2}.{1});"
+ template = "mkConnection({0}.{1},\n\t\t\t{2}.{1});"
name = self.get_iname(count)
ps = "pinmux.peripheral_side.%s" % sname
n = "{0}".format(name)
class sdmmc(PBase):
def slowimport(self):
- return " import sdcard_dummy :: *;"
+ return "import sdcard_dummy :: *;"
def num_axi_regs32(self):
return 13
def mkslow_peripheral(self):
- return " Ifc_sdcard_dummy sd{0} <- mksdcard_dummy();"
+ return "Ifc_sdcard_dummy sd{0} <- mksdcard_dummy();"
def _mk_connection(self, name=None, count=0):
return "sd{0}.slave"
ret = [PBase.mk_pincon(self, name, count)]
# special-case for gpio in, store in a temporary vector
plen = len(self.peripheral.pinspecs)
- template = " mkConnection({0}.{1},\n\t\t\t{2}.{1});"
+ template = "mkConnection({0}.{1},\n\t\t\t{2}.{1});"
sname = self.peripheral.iname().format(count)
name = self.get_iname(count)
ps = "pinmux.peripheral_side.%s" % sname
class twi(PBase):
def slowimport(self):
- return " import I2C_top :: *;"
+ return "import I2C_top :: *;"
def irq_name(self):
return "twi{0}_isint"
def slowifdecl(self):
- return " interface I2C_out twi{0}_out;\n" + \
- " method Bit#(1) %s;" % self.irq_name()
+ return "interface I2C_out twi{0}_out;\n" + \
+ "method Bit#(1) %s;" % self.irq_name()
def num_axi_regs32(self):
return 8
def mkslow_peripheral(self, size=0):
- return " I2C_IFC twi{0} <- mkI2CController();"
+ return "I2C_IFC twi{0} <- mkI2CController();"
def _mk_connection(self, name=None, count=0):
return "twi{0}.slave_i2c_axi"
def mk_ext_ifacedef(self, iname, inum):
name = self.get_iname(inum)
- return " method {0}_isint = {0}.isint;".format(name)
+ return "method {0}_isint = {0}.isint;".format(name)
def slowifdeclmux(self, name, inum):
sname = self.get_iname(inum)
- return " method Bit#(1) %s_isint;" % sname
+ return "method Bit#(1) %s_isint;" % sname
class uart(PBase):
def slowimport(self):
- return " import Uart_bs :: *;\n" + \
- " import RS232_modified::*;"
+ return "import Uart_bs :: *;\n" + \
+ "import RS232_modified::*;"
def slowifdecl(self):
- return " interface RS232 uart{0}_coe;\n" + \
- " method Bit#(1) uart{0}_intr;"
+ return "interface RS232 uart{0}_coe;\n" + \
+ "method Bit#(1) uart{0}_intr;"
def num_axi_regs32(self):
return 8
def mkslow_peripheral(self, size=0):
- return " Ifc_Uart_bs uart{0} <- \n" + \
- " mkUart_bs(clocked_by sp_clock,\n" + \
+ return "Ifc_Uart_bs uart{0} <- \n" + \
+ " mkUart_bs(clocked_by sp_clock,\n" + \
" reset_by sp_reset, sp_clock, sp_reset);"
def _mk_connection(self, name=None, count=0):
projects / pinmux.git / commitdiff