remove sram 4k wb bte/cti

diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.il b/experiments9/non_generated/full_core_4_4ksram_ls180.il
index 83848eb7e97e5fe4e6da4f2ca15a8724bd56601b..f056d58f347ba0a0cc89edde0031c4fa5a368703 100644 (file)
--- a/experiments9/non_generated/full_core_4_4ksram_ls180.il
+++ b/experiments9/non_generated/full_core_4_4ksram_ls180.il
@@ -237119,7 +237119,7 @@ module \logical_pipe2
   connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type }
   connect \output_muxid \muxid
 end
-attribute \src "ls180.v:4.1-11026.10"
+attribute \src "ls180.v:4.1-11018.10"
 attribute \cells_not_processed 1
 module \ls180
   attribute \src "ls180.v:10350.1-10368.4"
@@ -248610,24 +248610,24 @@ module \ls180
   wire \builder_sync_rhs_array_muxed6
   attribute \src "ls180.v:2011.6-2011.18"
   wire \builder_wait
-  attribute \src "ls180.v:5.19-5.23"
-  wire width 3 input 1 \eint
-  attribute \src "ls180.v:171.12-171.18"
+  attribute \src "ls180.v:9.19-9.23"
+  wire width 3 input 5 \eint
+  attribute \src "ls180.v:175.12-175.18"
   wire width 3 \eint_1
-  attribute \src "ls180.v:32.20-32.26"
-  wire width 16 input 28 \gpio_i
-  attribute \src "ls180.v:33.20-33.26"
-  wire width 16 output 29 \gpio_o
-  attribute \src "ls180.v:34.20-34.27"
-  wire width 16 output 30 \gpio_oe
-  attribute \src "ls180.v:35.14-35.21"
-  wire output 31 \i2c_scl
-  attribute \src "ls180.v:36.13-36.22"
-  wire input 32 \i2c_sda_i
-  attribute \src "ls180.v:37.14-37.23"
-  wire output 33 \i2c_sda_o
-  attribute \src "ls180.v:38.14-38.24"
-  wire output 34 \i2c_sda_oe
+  attribute \src "ls180.v:10.20-10.26"
+  wire width 16 input 6 \gpio_i
+  attribute \src "ls180.v:11.20-11.26"
+  wire width 16 output 7 \gpio_o
+  attribute \src "ls180.v:12.20-12.27"
+  wire width 16 output 8 \gpio_oe
+  attribute \src "ls180.v:39.14-39.21"
+  wire output 35 \i2c_scl
+  attribute \src "ls180.v:40.13-40.22"
+  wire input 36 \i2c_sda_i
+  attribute \src "ls180.v:41.14-41.23"
+  wire output 37 \i2c_sda_o
+  attribute \src "ls180.v:42.14-42.24"
+  wire output 38 \i2c_sda_oe
   attribute \src "ls180.v:49.13-49.21"
   wire input 45 \jtag_tck
   attribute \src "ls180.v:50.13-50.21"
@@ -248986,65 +248986,65 @@ module \ls180
   wire width 64 \main_libresocsim_libresoc2
   attribute \src "ls180.v:169.12-169.45"
   wire width 2 \main_libresocsim_libresoc_clk_sel
-  attribute \src "ls180.v:193.13-193.67"
+  attribute \src "ls180.v:176.13-176.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
-  attribute \src "ls180.v:194.13-194.67"
+  attribute \src "ls180.v:177.13-177.67"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
-  attribute \src "ls180.v:195.13-195.68"
+  attribute \src "ls180.v:178.13-178.68"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
-  attribute \src "ls180.v:196.6-196.61"
+  attribute \src "ls180.v:200.6-200.61"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
-  attribute \src "ls180.v:197.6-197.63"
+  attribute \src "ls180.v:201.6-201.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
-  attribute \src "ls180.v:198.6-198.63"
+  attribute \src "ls180.v:202.6-202.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
-  attribute \src "ls180.v:199.6-199.64"
+  attribute \src "ls180.v:203.6-203.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
-  attribute \src "ls180.v:172.6-172.64"
+  attribute \src "ls180.v:196.6-196.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
-  attribute \src "ls180.v:173.6-173.66"
+  attribute \src "ls180.v:197.6-197.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
-  attribute \src "ls180.v:174.6-174.66"
+  attribute \src "ls180.v:198.6-198.66"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
-  attribute \src "ls180.v:175.6-175.67"
+  attribute \src "ls180.v:199.6-199.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
-  attribute \src "ls180.v:181.13-181.68"
+  attribute \src "ls180.v:179.13-179.68"
   wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
-  attribute \src "ls180.v:190.12-190.68"
+  attribute \src "ls180.v:188.12-188.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
-  attribute \src "ls180.v:187.6-187.65"
+  attribute \src "ls180.v:185.6-185.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
-  attribute \src "ls180.v:189.6-189.63"
+  attribute \src "ls180.v:187.6-187.63"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
-  attribute \src "ls180.v:188.6-188.64"
+  attribute \src "ls180.v:186.6-186.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
-  attribute \src "ls180.v:191.12-191.68"
+  attribute \src "ls180.v:189.12-189.68"
   wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
-  attribute \src "ls180.v:182.13-182.71"
+  attribute \src "ls180.v:180.13-180.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
-  attribute \src "ls180.v:183.13-183.71"
+  attribute \src "ls180.v:181.13-181.71"
   wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
-  attribute \src "ls180.v:184.6-184.65"
+  attribute \src "ls180.v:182.6-182.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
-  attribute \src "ls180.v:186.6-186.65"
+  attribute \src "ls180.v:184.6-184.65"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
-  attribute \src "ls180.v:185.6-185.64"
+  attribute \src "ls180.v:183.6-183.64"
   wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
-  attribute \src "ls180.v:200.6-200.67"
+  attribute \src "ls180.v:171.6-171.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
-  attribute \src "ls180.v:202.6-202.68"
+  attribute \src "ls180.v:173.6-173.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
-  attribute \src "ls180.v:203.6-203.68"
+  attribute \src "ls180.v:174.6-174.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
-  attribute \src "ls180.v:201.6-201.68"
+  attribute \src "ls180.v:172.6-172.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
-  attribute \src "ls180.v:177.6-177.67"
+  attribute \src "ls180.v:192.6-192.67"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
-  attribute \src "ls180.v:179.6-179.68"
+  attribute \src "ls180.v:194.6-194.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
-  attribute \src "ls180.v:180.6-180.68"
+  attribute \src "ls180.v:195.6-195.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
-  attribute \src "ls180.v:178.6-178.68"
+  attribute \src "ls180.v:193.6-193.68"
   wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
   attribute \src "ls180.v:72.6-72.40"
   wire \main_libresocsim_libresoc_dbus_ack
@@ -252374,50 +252374,50 @@ module \ls180
   wire width 24 input 48 \nc
   attribute \src "ls180.v:338.6-338.13"
   wire \por_clk
-  attribute \src "ls180.v:13.19-13.22"
-  wire width 2 output 9 \pwm
-  attribute \src "ls180.v:176.12-176.17"
+  attribute \src "ls180.v:25.19-25.22"
+  wire width 2 output 21 \pwm
+  attribute \src "ls180.v:191.12-191.17"
   wire width 2 \pwm_1
-  attribute \src "ls180.v:6.13-6.23"
-  wire output 2 \sdcard_clk
-  attribute \src "ls180.v:7.13-7.25"
-  wire input 3 \sdcard_cmd_i
-  attribute \src "ls180.v:8.13-8.25"
-  wire output 4 \sdcard_cmd_o
-  attribute \src "ls180.v:9.13-9.26"
-  wire output 5 \sdcard_cmd_oe
-  attribute \src "ls180.v:10.19-10.32"
-  wire width 4 input 6 \sdcard_data_i
-  attribute \src "ls180.v:11.19-11.32"
-  wire width 4 output 7 \sdcard_data_o
-  attribute \src "ls180.v:12.13-12.27"
-  wire output 8 \sdcard_data_oe
-  attribute \src "ls180.v:18.20-18.27"
-  wire width 13 output 14 \sdram_a
-  attribute \src "ls180.v:27.19-27.27"
-  wire width 2 output 23 \sdram_ba
+  attribute \src "ls180.v:32.13-32.23"
+  wire output 28 \sdcard_clk
+  attribute \src "ls180.v:33.13-33.25"
+  wire input 29 \sdcard_cmd_i
+  attribute \src "ls180.v:34.13-34.25"
+  wire output 30 \sdcard_cmd_o
+  attribute \src "ls180.v:35.13-35.26"
+  wire output 31 \sdcard_cmd_oe
+  attribute \src "ls180.v:36.19-36.32"
+  wire width 4 input 32 \sdcard_data_i
+  attribute \src "ls180.v:37.19-37.32"
+  wire width 4 output 33 \sdcard_data_o
+  attribute \src "ls180.v:38.13-38.27"
+  wire output 34 \sdcard_data_oe
+  attribute \src "ls180.v:13.20-13.27"
+  wire width 13 output 9 \sdram_a
+  attribute \src "ls180.v:22.19-22.27"
+  wire width 2 output 18 \sdram_ba
+  attribute \src "ls180.v:19.13-19.24"
+  wire output 15 \sdram_cas_n
+  attribute \src "ls180.v:21.13-21.22"
+  wire output 17 \sdram_cke
   attribute \src "ls180.v:24.13-24.24"
-  wire output 20 \sdram_cas_n
-  attribute \src "ls180.v:26.13-26.22"
-  wire output 22 \sdram_cke
-  attribute \src "ls180.v:29.13-29.24"
-  wire output 25 \sdram_clock
-  attribute \src "ls180.v:192.6-192.19"
+  wire output 20 \sdram_clock
+  attribute \src "ls180.v:190.6-190.19"
   wire \sdram_clock_1
-  attribute \src "ls180.v:25.13-25.23"
-  wire output 21 \sdram_cs_n
-  attribute \src "ls180.v:28.19-28.27"
-  wire width 2 output 24 \sdram_dm
-  attribute \src "ls180.v:19.20-19.30"
-  wire width 16 input 15 \sdram_dq_i
-  attribute \src "ls180.v:20.20-20.30"
-  wire width 16 output 16 \sdram_dq_o
-  attribute \src "ls180.v:21.13-21.24"
-  wire output 17 \sdram_dq_oe
-  attribute \src "ls180.v:23.13-23.24"
-  wire output 19 \sdram_ras_n
-  attribute \src "ls180.v:22.13-22.23"
-  wire output 18 \sdram_we_n
+  attribute \src "ls180.v:20.13-20.23"
+  wire output 16 \sdram_cs_n
+  attribute \src "ls180.v:23.19-23.27"
+  wire width 2 output 19 \sdram_dm
+  attribute \src "ls180.v:14.20-14.30"
+  wire width 16 input 10 \sdram_dq_i
+  attribute \src "ls180.v:15.20-15.30"
+  wire width 16 output 11 \sdram_dq_o
+  attribute \src "ls180.v:16.13-16.24"
+  wire output 12 \sdram_dq_oe
+  attribute \src "ls180.v:18.13-18.24"
+  wire output 14 \sdram_ras_n
+  attribute \src "ls180.v:17.13-17.23"
+  wire output 13 \sdram_we_n
   attribute \src "ls180.v:2760.6-2760.15"
   wire \sdrio_clk
   attribute \src "ls180.v:2761.6-2761.17"
@@ -252556,22 +252556,22 @@ module \ls180
   wire \sdrio_clk_8
   attribute \src "ls180.v:2769.6-2769.17"
   wire \sdrio_clk_9
-  attribute \src "ls180.v:39.13-39.26"
-  wire output 35 \spimaster_clk
-  attribute \src "ls180.v:41.13-41.27"
-  wire output 37 \spimaster_cs_n
-  attribute \src "ls180.v:42.13-42.27"
-  wire input 38 \spimaster_miso
-  attribute \src "ls180.v:40.13-40.27"
-  wire output 36 \spimaster_mosi
-  attribute \src "ls180.v:14.13-14.26"
-  wire output 10 \spisdcard_clk
-  attribute \src "ls180.v:16.13-16.27"
-  wire output 12 \spisdcard_cs_n
-  attribute \src "ls180.v:17.13-17.27"
-  wire input 13 \spisdcard_miso
-  attribute \src "ls180.v:15.13-15.27"
-  wire output 11 \spisdcard_mosi
+  attribute \src "ls180.v:5.13-5.26"
+  wire output 1 \spimaster_clk
+  attribute \src "ls180.v:7.13-7.27"
+  wire output 3 \spimaster_cs_n
+  attribute \src "ls180.v:8.13-8.27"
+  wire input 4 \spimaster_miso
+  attribute \src "ls180.v:6.13-6.27"
+  wire output 2 \spimaster_mosi
+  attribute \src "ls180.v:26.13-26.26"
+  wire output 22 \spisdcard_clk
+  attribute \src "ls180.v:28.13-28.27"
+  wire output 24 \spisdcard_cs_n
+  attribute \src "ls180.v:29.13-29.27"
+  wire input 25 \spisdcard_miso
+  attribute \src "ls180.v:27.13-27.27"
+  wire output 23 \spisdcard_mosi
   attribute \src "ls180.v:43.13-43.20"
   wire input 39 \sys_clk
   attribute \src "ls180.v:336.6-336.15"
@@ -282158,7 +282158,7 @@ module \ls180
     connect \Y $xor$ls180.v:5383$1110_Y
   end
   attribute \module_not_derived 1
-  attribute \src "ls180.v:10606.13-11024.2"
+  attribute \src "ls180.v:10606.13-11016.2"
   cell \test_issuer \test_issuer
     connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck
     connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi
@@ -282535,8 +282535,6 @@ module \ls180
     connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
     connect \sram4k_0_wb__ack \main_libresocsim_libresoc_interface0_ack
     connect \sram4k_0_wb__adr \main_libresocsim_libresoc_interface0_adr
-    connect \sram4k_0_wb__bte \main_libresocsim_libresoc_interface0_bte
-    connect \sram4k_0_wb__cti \main_libresocsim_libresoc_interface0_cti
     connect \sram4k_0_wb__cyc \main_libresocsim_libresoc_interface0_cyc
     connect \sram4k_0_wb__dat_r \main_libresocsim_libresoc_interface0_dat_r
     connect \sram4k_0_wb__dat_w \main_libresocsim_libresoc_interface0_dat_w
@@ -282546,8 +282544,6 @@ module \ls180
     connect \sram4k_0_wb__we \main_libresocsim_libresoc_interface0_we
     connect \sram4k_1_wb__ack \main_libresocsim_libresoc_interface1_ack
     connect \sram4k_1_wb__adr \main_libresocsim_libresoc_interface1_adr
-    connect \sram4k_1_wb__bte \main_libresocsim_libresoc_interface1_bte
-    connect \sram4k_1_wb__cti \main_libresocsim_libresoc_interface1_cti
     connect \sram4k_1_wb__cyc \main_libresocsim_libresoc_interface1_cyc
     connect \sram4k_1_wb__dat_r \main_libresocsim_libresoc_interface1_dat_r
     connect \sram4k_1_wb__dat_w \main_libresocsim_libresoc_interface1_dat_w
@@ -282557,8 +282553,6 @@ module \ls180
     connect \sram4k_1_wb__we \main_libresocsim_libresoc_interface1_we
     connect \sram4k_2_wb__ack \main_libresocsim_libresoc_interface2_ack
     connect \sram4k_2_wb__adr \main_libresocsim_libresoc_interface2_adr
-    connect \sram4k_2_wb__bte \main_libresocsim_libresoc_interface2_bte
-    connect \sram4k_2_wb__cti \main_libresocsim_libresoc_interface2_cti
     connect \sram4k_2_wb__cyc \main_libresocsim_libresoc_interface2_cyc
     connect \sram4k_2_wb__dat_r \main_libresocsim_libresoc_interface2_dat_r
     connect \sram4k_2_wb__dat_w \main_libresocsim_libresoc_interface2_dat_w
@@ -282568,8 +282562,6 @@ module \ls180
     connect \sram4k_2_wb__we \main_libresocsim_libresoc_interface2_we
     connect \sram4k_3_wb__ack \main_libresocsim_libresoc_interface3_ack
     connect \sram4k_3_wb__adr \main_libresocsim_libresoc_interface3_adr
-    connect \sram4k_3_wb__bte \main_libresocsim_libresoc_interface3_bte
-    connect \sram4k_3_wb__cti \main_libresocsim_libresoc_interface3_cti
     connect \sram4k_3_wb__cyc \main_libresocsim_libresoc_interface3_cyc
     connect \sram4k_3_wb__dat_r \main_libresocsim_libresoc_interface3_dat_r
     connect \sram4k_3_wb__dat_w \main_libresocsim_libresoc_interface3_dat_w
@@ -295591,11 +295583,6 @@ module \ls180
     assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3]
     assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3]
     sync posedge \sdrio_clk
-      update \sdcard_clk $0\sdcard_clk[0:0]
-      update \sdcard_cmd_o $0\sdcard_cmd_o[0:0]
-      update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0]
-      update \sdcard_data_o $0\sdcard_data_o[3:0]
-      update \sdcard_data_oe $0\sdcard_data_oe[0:0]
       update \sdram_a $0\sdram_a[12:0]
       update \sdram_dq_o $0\sdram_dq_o[15:0]
       update \sdram_dq_oe $0\sdram_dq_oe[0:0]
@@ -295607,6 +295594,11 @@ module \ls180
       update \sdram_ba $0\sdram_ba[1:0]
       update \sdram_dm $0\sdram_dm[1:0]
       update \sdram_clock $0\sdram_clock[0:0]
+      update \sdcard_clk $0\sdcard_clk[0:0]
+      update \sdcard_cmd_o $0\sdcard_cmd_o[0:0]
+      update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0]
+      update \sdcard_data_o $0\sdcard_data_o[3:0]
+      update \sdcard_data_oe $0\sdcard_data_oe[0:0]
       update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0]
       update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0]
       update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0]
@@ -295629,14 +295621,14 @@ module \ls180
   end
   attribute \src "ls180.v:7702.1-10346.4"
   process $proc$ls180.v:7702$2573
+    assign $0\spimaster_clk[0:0] \spimaster_clk
+    assign $0\spimaster_mosi[0:0] \spimaster_mosi
+    assign { } { }
     assign $0\pwm[1:0] \pwm
     assign $0\spisdcard_clk[0:0] \spisdcard_clk
     assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
     assign { } { }
     assign $0\uart_tx[0:0] \uart_tx
-    assign $0\spimaster_clk[0:0] \spimaster_clk
-    assign $0\spimaster_mosi[0:0] \spimaster_mosi
-    assign { } { }
     assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
     assign { } { }
     assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage
@@ -300209,14 +300201,14 @@ module \ls180
         assign $0\main_libresocsim_scratch_storage[31:0] 305419896
         assign $0\main_libresocsim_scratch_re[0:0] 1'0
         assign $0\main_libresocsim_bus_errors[31:0] 0
+        assign $0\spimaster_clk[0:0] 1'0
+        assign $0\spimaster_mosi[0:0] 1'0
+        assign $0\spimaster_cs_n[0:0] 1'0
         assign $0\pwm[1:0] 2'00
         assign $0\spisdcard_clk[0:0] 1'0
         assign $0\spisdcard_mosi[0:0] 1'0
         assign $0\spisdcard_cs_n[0:0] 1'0
         assign $0\uart_tx[0:0] 1'1
-        assign $0\spimaster_clk[0:0] 1'0
-        assign $0\spimaster_mosi[0:0] 1'0
-        assign $0\spimaster_cs_n[0:0] 1'0
         assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0
         assign $0\main_libresocsim_load_storage[31:0] 0
         assign $0\main_libresocsim_load_re[0:0] 1'0
@@ -300504,14 +300496,14 @@ module \ls180
       case 
     end
     sync posedge \sys_clk_1
+      update \spimaster_clk $0\spimaster_clk[0:0]
+      update \spimaster_mosi $0\spimaster_mosi[0:0]
+      update \spimaster_cs_n $0\spimaster_cs_n[0:0]
       update \pwm $0\pwm[1:0]
       update \spisdcard_clk $0\spisdcard_clk[0:0]
       update \spisdcard_mosi $0\spisdcard_mosi[0:0]
       update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
       update \uart_tx $0\uart_tx[0:0]
-      update \spimaster_clk $0\spimaster_clk[0:0]
-      update \spimaster_mosi $0\spimaster_mosi[0:0]
-      update \spimaster_cs_n $0\spimaster_cs_n[0:0]
       update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
       update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
       update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]