construct an MSRSpec in PortInterfaceBase (not used yet)

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 51a6abef2b5bb82ced399d9efadbf09686c745dc..7e92e9674ab07f477f1af71b3b82128c8b3a5cfc 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -228,6 +228,7 @@ class PortInterfaceBase(Elaboratable):
         pr = ~pi.priv_mode
         dr = pi.virt_mode   # not yet used
         sf = pi.mode_32bit   # not yet used
+        msr = MSRSpec(pr=pr, dr=dr, sf=sf)
 
         # detect busy "edge"
         busy_delay = Signal()