if (ctx->current_saved_cs)
si_saved_cs_reference(&ctx->current_saved_cs, NULL);
- si_begin_new_cs(ctx);
+ si_begin_new_gfx_cs(ctx);
ctx->gfx_flush_in_progress = false;
}
-static void si_begin_cs_debug(struct si_context *ctx)
+static void si_begin_gfx_cs_debug(struct si_context *ctx)
{
static const uint32_t zeros[1];
assert(!ctx->current_saved_cs);
RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
}
-void si_begin_new_cs(struct si_context *ctx)
+void si_begin_new_gfx_cs(struct si_context *ctx)
{
if (ctx->is_debug)
- si_begin_cs_debug(ctx);
+ si_begin_gfx_cs_debug(ctx);
/* Flush read caches at the beginning of CS not flushed by the kernel. */
if (ctx->b.chip_class >= CIK)
sctx->sample_mask.sample_mask = 0xffff;
/* these must be last */
- si_begin_new_cs(sctx);
+ si_begin_new_gfx_cs(sctx);
if (sctx->b.chip_class >= GFX9) {
sctx->wait_mem_scratch = (struct r600_resource*)
void si_destroy_saved_cs(struct si_saved_cs *scs);
void si_flush_gfx_cs(void *context, unsigned flags,
struct pipe_fence_handle **fence);
-void si_begin_new_cs(struct si_context *ctx);
+void si_begin_new_gfx_cs(struct si_context *ctx);
void si_need_gfx_cs_space(struct si_context *ctx);
/* si_compute.c */