src/gallium/drivers/radeonsi/si_hw_context.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "radeon/r600_cs.h"
  26
  27 #include "util/os_time.h"
  28
  29 void si_destroy_saved_cs(struct si_saved_cs *scs)
  30 {
  31         si_clear_saved_cs(&scs->gfx);
  32         r600_resource_reference(&scs->trace_buf, NULL);
  33         free(scs);
  34 }
  35
  36 /* initialize */
  37 void si_need_gfx_cs_space(struct si_context *ctx)
  38 {
  39         struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
  40
  41         /* There is no need to flush the DMA IB here, because
  42          * r600_need_dma_space always flushes the GFX IB if there is
  43          * a conflict, which means any unflushed DMA commands automatically
  44          * precede the GFX IB (= they had no dependency on the GFX IB when
  45          * they were submitted).
  46          */
  47
  48         /* There are two memory usage counters in the winsys for all buffers
  49          * that have been added (cs_add_buffer) and two counters in the pipe
  50          * driver for those that haven't been added yet.
  51          */
  52         if (unlikely(!radeon_cs_memory_below_limit(ctx->b.screen, ctx->b.gfx.cs,
  53                                                    ctx->b.vram, ctx->b.gtt))) {
  54                 ctx->b.gtt = 0;
  55                 ctx->b.vram = 0;
  56                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  57                 return;
  58         }
  59         ctx->b.gtt = 0;
  60         ctx->b.vram = 0;
  61
  62         /* If the IB is sufficiently large, don't count the space needed
  63          * and just flush if there is not enough space left.
  64          *
  65          * Also reserve space for stopping queries at the end of IB, because
  66          * the number of active queries is mostly unlimited.
  67          */
  68         unsigned need_dwords = 2048 + ctx->b.num_cs_dw_queries_suspend;
  69         if (!ctx->b.ws->cs_check_space(cs, need_dwords))
  70                 si_flush_gfx_cs(ctx, PIPE_FLUSH_ASYNC, NULL);
  71 }
  72
  73 void si_flush_gfx_cs(void *context, unsigned flags,
  74                      struct pipe_fence_handle **fence)
  75 {
  76         struct si_context *ctx = context;
  77         struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
  78         struct radeon_winsys *ws = ctx->b.ws;
  79
  80         if (ctx->gfx_flush_in_progress)
  81                 return;
  82
  83         if (!radeon_emitted(cs, ctx->b.initial_gfx_cs_size))
  84                 return;
  85
  86         if (si_check_device_reset(&ctx->b))
  87                 return;
  88
  89         if (ctx->screen->debug_flags & DBG(CHECK_VM))
  90                 flags &= ~PIPE_FLUSH_ASYNC;
  91
  92         /* If the state tracker is flushing the GFX IB, r600_flush_from_st is
  93          * responsible for flushing the DMA IB and merging the fences from both.
  94          * This code is only needed when the driver flushes the GFX IB
  95          * internally, and it never asks for a fence handle.
  96          */
  97         if (radeon_emitted(ctx->b.dma.cs, 0)) {
  98                 assert(fence == NULL); /* internal flushes only */
  99                 si_flush_dma_cs(ctx, flags, NULL);
 100         }
 101
 102         ctx->gfx_flush_in_progress = true;
 103
 104         if (!LIST_IS_EMPTY(&ctx->b.active_queries))
 105                 si_suspend_queries(&ctx->b);
 106
 107         ctx->streamout.suspended = false;
 108         if (ctx->streamout.begin_emitted) {
 109                 si_emit_streamout_end(ctx);
 110                 ctx->streamout.suspended = true;
 111         }
 112
 113         ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
 114                         SI_CONTEXT_PS_PARTIAL_FLUSH;
 115
 116         /* DRM 3.1.0 doesn't flush TC for VI correctly. */
 117         if (ctx->b.chip_class == VI && ctx->b.screen->info.drm_minor <= 1)
 118                 ctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2 |
 119                                 SI_CONTEXT_INV_VMEM_L1;
 120
 121         si_emit_cache_flush(ctx);
 122
 123         if (ctx->current_saved_cs) {
 124                 si_trace_emit(ctx);
 125                 si_log_hw_flush(ctx);
 126
 127                 /* Save the IB for debug contexts. */
 128                 si_save_cs(ws, cs, &ctx->current_saved_cs->gfx, true);
 129                 ctx->current_saved_cs->flushed = true;
 130                 ctx->current_saved_cs->time_flush = os_time_get_nano();
 131         }
 132
 133         /* Flush the CS. */
 134         ws->cs_flush(cs, flags, &ctx->b.last_gfx_fence);
 135         if (fence)
 136                 ws->fence_reference(fence, ctx->b.last_gfx_fence);
 137
 138         /* This must be after cs_flush returns, since the context's API
 139          * thread can concurrently read this value in si_fence_finish. */
 140         ctx->b.num_gfx_cs_flushes++;
 141
 142         /* Check VM faults if needed. */
 143         if (ctx->screen->debug_flags & DBG(CHECK_VM)) {
 144                 /* Use conservative timeout 800ms, after which we won't wait any
 145                  * longer and assume the GPU is hung.
 146                  */
 147                 ctx->b.ws->fence_wait(ctx->b.ws, ctx->b.last_gfx_fence, 800*1000*1000);
 148
 149                 si_check_vm_faults(&ctx->b, &ctx->current_saved_cs->gfx, RING_GFX);
 150         }
 151
 152         if (ctx->current_saved_cs)
 153                 si_saved_cs_reference(&ctx->current_saved_cs, NULL);
 154
 155         si_begin_new_gfx_cs(ctx);
 156         ctx->gfx_flush_in_progress = false;
 157 }
 158
 159 static void si_begin_gfx_cs_debug(struct si_context *ctx)
 160 {
 161         static const uint32_t zeros[1];
 162         assert(!ctx->current_saved_cs);
 163
 164         ctx->current_saved_cs = calloc(1, sizeof(*ctx->current_saved_cs));
 165         if (!ctx->current_saved_cs)
 166                 return;
 167
 168         pipe_reference_init(&ctx->current_saved_cs->reference, 1);
 169
 170         ctx->current_saved_cs->trace_buf = (struct r600_resource*)
 171                                  pipe_buffer_create(ctx->b.b.screen, 0,
 172                                                     PIPE_USAGE_STAGING, 8);
 173         if (!ctx->current_saved_cs->trace_buf) {
 174                 free(ctx->current_saved_cs);
 175                 ctx->current_saved_cs = NULL;
 176                 return;
 177         }
 178
 179         pipe_buffer_write_nooverlap(&ctx->b.b, &ctx->current_saved_cs->trace_buf->b.b,
 180                                     0, sizeof(zeros), zeros);
 181         ctx->current_saved_cs->trace_id = 0;
 182
 183         si_trace_emit(ctx);
 184
 185         radeon_add_to_buffer_list(&ctx->b, &ctx->b.gfx, ctx->current_saved_cs->trace_buf,
 186                               RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
 187 }
 188
 189 void si_begin_new_gfx_cs(struct si_context *ctx)
 190 {
 191         if (ctx->is_debug)
 192                 si_begin_gfx_cs_debug(ctx);
 193
 194         /* Flush read caches at the beginning of CS not flushed by the kernel. */
 195         if (ctx->b.chip_class >= CIK)
 196                 ctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
 197                                 SI_CONTEXT_INV_ICACHE;
 198
 199         ctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS;
 200
 201         /* set all valid group as dirty so they get reemited on
 202          * next draw command
 203          */
 204         si_pm4_reset_emitted(ctx);
 205
 206         /* The CS initialization should be emitted before everything else. */
 207         si_pm4_emit(ctx, ctx->init_config);
 208         if (ctx->init_config_gs_rings)
 209                 si_pm4_emit(ctx, ctx->init_config_gs_rings);
 210
 211         if (ctx->queued.named.ls)
 212                 ctx->prefetch_L2_mask |= SI_PREFETCH_LS;
 213         if (ctx->queued.named.hs)
 214                 ctx->prefetch_L2_mask |= SI_PREFETCH_HS;
 215         if (ctx->queued.named.es)
 216                 ctx->prefetch_L2_mask |= SI_PREFETCH_ES;
 217         if (ctx->queued.named.gs)
 218                 ctx->prefetch_L2_mask |= SI_PREFETCH_GS;
 219         if (ctx->queued.named.vs)
 220                 ctx->prefetch_L2_mask |= SI_PREFETCH_VS;
 221         if (ctx->queued.named.ps)
 222                 ctx->prefetch_L2_mask |= SI_PREFETCH_PS;
 223         if (ctx->vb_descriptors_buffer && ctx->vertex_elements)
 224                 ctx->prefetch_L2_mask |= SI_PREFETCH_VBO_DESCRIPTORS;
 225
 226         /* CLEAR_STATE disables all colorbuffers, so only enable bound ones. */
 227         bool has_clear_state = ctx->screen->has_clear_state;
 228         if (has_clear_state) {
 229                 ctx->framebuffer.dirty_cbufs =
 230                          u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs);
 231                 /* CLEAR_STATE disables the zbuffer, so only enable it if it's bound. */
 232                 ctx->framebuffer.dirty_zsbuf = ctx->framebuffer.state.zsbuf != NULL;
 233         } else {
 234                 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8);
 235                 ctx->framebuffer.dirty_zsbuf = true;
 236         }
 237         /* This should always be marked as dirty to set the framebuffer scissor
 238          * at least. */
 239         si_mark_atom_dirty(ctx, &ctx->framebuffer.atom);
 240
 241         si_mark_atom_dirty(ctx, &ctx->clip_regs);
 242         /* CLEAR_STATE sets zeros. */
 243         if (!has_clear_state || ctx->clip_state.any_nonzeros)
 244                 si_mark_atom_dirty(ctx, &ctx->clip_state.atom);
 245         ctx->msaa_sample_locs.nr_samples = 0;
 246         si_mark_atom_dirty(ctx, &ctx->msaa_sample_locs.atom);
 247         si_mark_atom_dirty(ctx, &ctx->msaa_config);
 248         /* CLEAR_STATE sets 0xffff. */
 249         if (!has_clear_state || ctx->sample_mask.sample_mask != 0xffff)
 250                 si_mark_atom_dirty(ctx, &ctx->sample_mask.atom);
 251         si_mark_atom_dirty(ctx, &ctx->cb_render_state);
 252         /* CLEAR_STATE sets zeros. */
 253         if (!has_clear_state || ctx->blend_color.any_nonzeros)
 254                 si_mark_atom_dirty(ctx, &ctx->blend_color.atom);
 255         si_mark_atom_dirty(ctx, &ctx->db_render_state);
 256         if (ctx->b.chip_class >= GFX9)
 257                 si_mark_atom_dirty(ctx, &ctx->dpbb_state);
 258         si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
 259         si_mark_atom_dirty(ctx, &ctx->spi_map);
 260         si_mark_atom_dirty(ctx, &ctx->streamout.enable_atom);
 261         si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
 262         si_all_descriptors_begin_new_cs(ctx);
 263         si_all_resident_buffers_begin_new_cs(ctx);
 264
 265         ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 266         ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 267         ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
 268         si_mark_atom_dirty(ctx, &ctx->scissors.atom);
 269         si_mark_atom_dirty(ctx, &ctx->viewports.atom);
 270
 271         si_mark_atom_dirty(ctx, &ctx->scratch_state);
 272         if (ctx->scratch_buffer) {
 273                 si_context_add_resource_size(&ctx->b.b,
 274                                              &ctx->scratch_buffer->b.b);
 275         }
 276
 277         if (ctx->streamout.suspended) {
 278                 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
 279                 si_streamout_buffers_dirty(ctx);
 280         }
 281
 282         if (!LIST_IS_EMPTY(&ctx->b.active_queries))
 283                 si_resume_queries(&ctx->b);
 284
 285         assert(!ctx->b.gfx.cs->prev_dw);
 286         ctx->b.initial_gfx_cs_size = ctx->b.gfx.cs->current.cdw;
 287
 288         /* Invalidate various draw states so that they are emitted before
 289          * the first draw call. */
 290         si_invalidate_draw_sh_constants(ctx);
 291         ctx->last_index_size = -1;
 292         ctx->last_primitive_restart_en = -1;
 293         ctx->last_restart_index = SI_RESTART_INDEX_UNKNOWN;
 294         ctx->last_gs_out_prim = -1;
 295         ctx->last_prim = -1;
 296         ctx->last_multi_vgt_param = -1;
 297         ctx->last_rast_prim = -1;
 298         ctx->last_sc_line_stipple = ~0;
 299         ctx->last_vs_state = ~0;
 300         ctx->last_ls = NULL;
 301         ctx->last_tcs = NULL;
 302         ctx->last_tes_sh_base = -1;
 303         ctx->last_num_tcs_input_cp = -1;
 304
 305         ctx->cs_shader_state.initialized = false;
 306 }