rename spr1/spr2 to fast1/fast2 in branch

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 27076a56e763e9ec6ad2f58bab941d7aeda79e5a..9d7c2a543d8eeb85480679bef826fd4f3c1f3397 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -57,8 +57,8 @@ class BranchMainStage(PipeModBase):
         comb = m.d.comb
         op = self.i.ctx.op
         lk = op.lk # see PowerDecode2 as to why this is done
-        cr, cia, ctr, spr1 = self.i.cr, self.i.cia, self.i.ctr, self.i.spr1
-        spr2 = self.i.spr2
+        cr, cia, ctr, fast1 = self.i.cr, self.i.cia, self.i.ctr, self.i.fast1
+        fast2 = self.i.fast2
         nia_o, lr_o, ctr_o = self.o.nia, self.o.lr, self.o.ctr
 
         # obtain relevant instruction field AA, "Absolute Address" mode
@@ -135,9 +135,9 @@ class BranchMainStage(PipeModBase):
             with m.Case(InternalOp.OP_BCREG):
                 xo = self.fields.FormXL.XO[0:-1]
                 with m.If(xo[9] & ~xo[5]):
-                    comb += br_imm_addr.eq(Cat(Const(0, 2), spr1[2:]))
+                    comb += br_imm_addr.eq(Cat(Const(0, 2), fast1[2:]))
                 with m.Else():
-                    comb += br_imm_addr.eq(Cat(Const(0, 2), spr2[2:]))
+                    comb += br_imm_addr.eq(Cat(Const(0, 2), fast2[2:]))
                 comb += br_taken.eq(bc_taken)
                 comb += ctr_o.ok.eq(ctr_write)
 

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index 1ebfc05bfbdab5ed85b0a6a91b455562fb8b9d57..fb01775d65eb7c0ce56e162b42800e72f8eaeb17 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -31,29 +31,29 @@ class BranchInputData(IntegerData):
     # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
     # this involves the *decode* unit selecting the register, based
     # on detecting the operand being bcctr, bclr or bctar
-    regspec = [('FAST', 'spr1', '0:63'), # see table above, SPR1
-               ('FAST', 'spr2', '0:63'), # see table above, SPR2
+    regspec = [('FAST', 'fast1', '0:63'), # see table above, SPR1
+               ('FAST', 'fast2', '0:63'), # see table above, SPR2
                ('CR', 'cr_a', '0:3'),    # Condition Register(s) CR0-7
                ('FAST', 'cia', '0:63')]  # Current Instruction Address
     def __init__(self, pspec):
         super().__init__(pspec, False)
 
         # convenience variables.  not all of these are used at once
-        self.ctr = self.spr1
-        self.lr = self.tar = self.spr2
+        self.ctr = self.fast1
+        self.lr = self.tar = self.fast2
         self.cr = self.cr_a
 
 
 class BranchOutputData(IntegerData):
-    regspec = [('FAST', 'spr1', '0:63'),
-               ('FAST', 'spr2', '0:63'),
+    regspec = [('FAST', 'fast1', '0:63'),
+               ('FAST', 'fast2', '0:63'),
                ('FAST', 'nia', '0:63')]
     def __init__(self, pspec):
         super().__init__(pspec, True)
 
         # convenience variables.
-        self.ctr = self.spr1
-        self.lr = self.tar = self.spr2
+        self.ctr = self.fast1
+        self.lr = self.tar = self.fast2
 
 
 class BranchPipeSpec(CommonPipeSpec):