also add blackboxes spblock512* etc.

diff --git a/experiments9/freepdk_c4m45/Makefile b/experiments9/freepdk_c4m45/Makefile
index 1a2db134c5ebc6c427d6dbd3fa432fcdc28cc86b..799c6f273f2481b376aef4ca52052e016e44a168 100755 (executable)
--- a/experiments9/freepdk_c4m45/Makefile
+++ b/experiments9/freepdk_c4m45/Makefile
@@ -5,6 +5,11 @@
        PHYSICAL_SYNTHESIS = Coriolis
                DESIGN_KIT = FreePDK_C4M45
              YOSYS_FLATTEN = No
+         YOSYS_BLACKBOXES = pll \
+                           spblock512w64b8w_0 \
+                           spblock512w64b8w_1 \
+                           spblock512w64b8w_2 \
+                           spblock512w64b8w_3
 #            YOSYS_SET_TOP = Yes
                     CHIP  = chip
                     CORE  = ls180
@@ -46,3 +51,5 @@ cif:             chip_r.cif
 
 view:      cgt-chip_r
 sim:       asimut-ls180_r
+
+

diff --git a/experiments9/tsmc_c018/Makefile b/experiments9/tsmc_c018/Makefile
index 0713bdb4c08f85d38aa354515fe76356688848cd..25d0b31692123f64f7ccb3d0435aebf41251f50f 100755 (executable)
--- a/experiments9/tsmc_c018/Makefile
+++ b/experiments9/tsmc_c018/Makefile
@@ -4,7 +4,11 @@
                DESIGN_KIT = FlexLib018
 #              DESIGN_KIT = cmos45
             YOSYS_FLATTEN = No
-        YOSYS_BLACKBOXES = spblock_512w64b8w pll
+         YOSYS_BLACKBOXES = pll \
+                           spblock512w64b8w_0 \
+                           spblock512w64b8w_1 \
+                           spblock512w64b8w_2 \
+                           spblock512w64b8w_3
 #            YOSYS_SET_TOP = Yes
                     CHIP  = chip
                     CORE  = ls180
@@ -47,3 +51,7 @@ cif:             chip_r.cif
 
 view:      cgt-chip_r
 sim:       asimut-ls180_r
+
+
+
+