rename ALUPipeData to LogicalPipeData

diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py
index 41183b5bc43a4eecce857e4b9289a273de124c29..17a5733526a85ac16ac871d8c41f5fb847195bd0 100644 (file)
--- a/src/soc/fu/logical/main_stage.py
+++ b/src/soc/fu/logical/main_stage.py
@@ -8,7 +8,7 @@
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
 from nmutil.clz import CLZ
-from soc.fu.logical.pipe_data import ALUInputData
+from soc.fu.logical.pipe_data import LogicalInputData
 from soc.fu.alu.pipe_data import ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 65233fde69c58f80ecf651e9d1c23189b68b8f04..3b1b13513a4a6b07ea549623f02c42a6c4821335 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -3,7 +3,7 @@ from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.alu.pipe_data import IntegerData
 
 
-class ALUInputData(IntegerData):
+class LogicalInputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA