+++ /dev/null
-[root]
-type=Root
-children=system
-full_system=false
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem l2c membus physmem toL2Bus
-boot_osflags=a
-clock=1000
-init_param=0
-kernel=
-load_addr_mask=1099511627775
-mem_mode=timing
-mem_ranges=
-memories=system.funcmem system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[1]
-
-[system.cpu0]
-type=MemTest
-children=l1c
-atomic=false
-clock=500
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=10
-progress_interval=10000
-suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.cpu0.l1c.cpu_side
-
-[system.cpu0.l1c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=4
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=32768
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu0.test
-mem_side=system.toL2Bus.slave[0]
-
-[system.cpu1]
-type=MemTest
-children=l1c
-atomic=false
-clock=500
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=10
-progress_interval=10000
-suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.cpu1.l1c.cpu_side
-
-[system.cpu1.l1c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=4
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=32768
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu1.test
-mem_side=system.toL2Bus.slave[1]
-
-[system.cpu2]
-type=MemTest
-children=l1c
-atomic=false
-clock=500
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=10
-progress_interval=10000
-suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.cpu2.l1c.cpu_side
-
-[system.cpu2.l1c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=4
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=32768
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu2.test
-mem_side=system.toL2Bus.slave[2]
-
-[system.cpu3]
-type=MemTest
-children=l1c
-atomic=false
-clock=500
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=10
-progress_interval=10000
-suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.cpu3.l1c.cpu_side
-
-[system.cpu3.l1c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=4
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=32768
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu3.test
-mem_side=system.toL2Bus.slave[3]
-
-[system.cpu4]
-type=MemTest
-children=l1c
-atomic=false
-clock=500
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=10
-progress_interval=10000
-suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.cpu4.l1c.cpu_side
-
-[system.cpu4.l1c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=4
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=32768
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu4.test
-mem_side=system.toL2Bus.slave[4]
-
-[system.cpu5]
-type=MemTest
-children=l1c
-atomic=false
-clock=500
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=10
-progress_interval=10000
-suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.cpu5.l1c.cpu_side
-
-[system.cpu5.l1c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=4
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=32768
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu5.test
-mem_side=system.toL2Bus.slave[5]
-
-[system.cpu6]
-type=MemTest
-children=l1c
-atomic=false
-clock=500
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=10
-progress_interval=10000
-suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.cpu6.l1c.cpu_side
-
-[system.cpu6.l1c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=4
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=32768
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu6.test
-mem_side=system.toL2Bus.slave[6]
-
-[system.cpu7]
-type=MemTest
-children=l1c
-atomic=false
-clock=500
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=10
-progress_interval=10000
-suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.cpu7.l1c.cpu_side
-
-[system.cpu7.l1c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=4
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-size=32768
-system=system
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu7.test
-mem_side=system.toL2Bus.slave[7]
-
-[system.funcbus]
-type=NoncoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1000
-conf_table_reported=false
-in_addr_map=false
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.funcbus.master[0]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-clock=500
-forward_snoops=true
-hit_latency=20
-is_top_level=false
-max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
-size=65536
-system=system
-tgts_per_mshr=12
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
-
-[system.membus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-system=system
-use_default_range=false
-width=16
-master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1000
-conf_table_reported=false
-in_addr_map=true
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-zero=false
-port=system.membus.master[0]
-
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=500
-header_cycles=1
-system=system
-use_default_range=false
-width=16
-master=system.l2c.cpu_side
-slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
-
+++ /dev/null
-system.cpu6: completed 10000 read, 5435 write accesses @79021500
-system.cpu0: completed 10000 read, 5363 write accesses @79194500
-system.cpu7: completed 10000 read, 5392 write accesses @79770500
-system.cpu2: completed 10000 read, 5375 write accesses @80689500
-system.cpu1: completed 10000 read, 5373 write accesses @81623500
-system.cpu4: completed 10000 read, 5458 write accesses @81916000
-system.cpu5: completed 10000 read, 5507 write accesses @81975000
-system.cpu3: completed 10000 read, 5421 write accesses @82381000
-system.cpu2: completed 20000 read, 10678 write accesses @153864500
-system.cpu0: completed 20000 read, 10854 write accesses @154789000
-system.cpu7: completed 20000 read, 10817 write accesses @154953500
-system.cpu1: completed 20000 read, 10781 write accesses @155855500
-system.cpu3: completed 20000 read, 10799 write accesses @157033000
-system.cpu4: completed 20000 read, 10854 write accesses @157158000
-system.cpu6: completed 20000 read, 10878 write accesses @157795000
-system.cpu5: completed 20000 read, 10963 write accesses @159866500
-system.cpu0: completed 30000 read, 16180 write accesses @228385000
-system.cpu2: completed 30000 read, 15995 write accesses @229109500
-system.cpu7: completed 30000 read, 16232 write accesses @231170000
-system.cpu1: completed 30000 read, 16165 write accesses @231658500
-system.cpu4: completed 30000 read, 16252 write accesses @232783000
-system.cpu6: completed 30000 read, 16228 write accesses @233712000
-system.cpu3: completed 30000 read, 16226 write accesses @236523000
-system.cpu5: completed 30000 read, 16456 write accesses @239602000
-system.cpu0: completed 40000 read, 21598 write accesses @305262000
-system.cpu2: completed 40000 read, 21332 write accesses @306571000
-system.cpu1: completed 40000 read, 21599 write accesses @307778500
-system.cpu4: completed 40000 read, 21599 write accesses @307971000
-system.cpu7: completed 40000 read, 21551 write accesses @308441000
-system.cpu6: completed 40000 read, 21597 write accesses @310397000
-system.cpu3: completed 40000 read, 21704 write accesses @312891000
-system.cpu5: completed 40000 read, 21914 write accesses @315565000
-system.cpu4: completed 50000 read, 26891 write accesses @381925000
-system.cpu0: completed 50000 read, 26990 write accesses @382095500
-system.cpu2: completed 50000 read, 26686 write accesses @382917500
-system.cpu1: completed 50000 read, 26983 write accesses @384289000
-system.cpu6: completed 50000 read, 27066 write accesses @384539000
-system.cpu7: completed 50000 read, 26943 write accesses @385136500
-system.cpu3: completed 50000 read, 27037 write accesses @389922000
-system.cpu5: completed 50000 read, 27423 write accesses @393691500
-system.cpu6: completed 60000 read, 32353 write accesses @457634500
-system.cpu4: completed 60000 read, 32228 write accesses @457992000
-system.cpu1: completed 60000 read, 32457 write accesses @460714000
-system.cpu2: completed 60000 read, 32178 write accesses @461196500
-system.cpu0: completed 60000 read, 32542 write accesses @461690000
-system.cpu7: completed 60000 read, 32302 write accesses @462388500
-system.cpu3: completed 60000 read, 32488 write accesses @466103000
-system.cpu5: completed 60000 read, 32744 write accesses @469778000
-system.cpu6: completed 70000 read, 37747 write accesses @533745000
-system.cpu2: completed 70000 read, 37532 write accesses @535320500
-system.cpu4: completed 70000 read, 37773 write accesses @535591500
-system.cpu7: completed 70000 read, 37639 write accesses @538124500
-system.cpu0: completed 70000 read, 37909 write accesses @538334500
-system.cpu1: completed 70000 read, 37921 write accesses @541231500
-system.cpu3: completed 70000 read, 37871 write accesses @542226500
-system.cpu5: completed 70000 read, 38229 write accesses @548322500
-system.cpu4: completed 80000 read, 42983 write accesses @610769500
-system.cpu6: completed 80000 read, 43020 write accesses @610776000
-system.cpu2: completed 80000 read, 42982 write accesses @611661000
-system.cpu0: completed 80000 read, 43374 write accesses @615085500
-system.cpu1: completed 80000 read, 43250 write accesses @615627500
-system.cpu7: completed 80000 read, 43033 write accesses @615746000
-system.cpu3: completed 80000 read, 43154 write accesses @619760000
-system.cpu5: completed 80000 read, 43738 write accesses @625688001
-system.cpu6: completed 90000 read, 48339 write accesses @685422000
-system.cpu2: completed 90000 read, 48272 write accesses @687608500
-system.cpu4: completed 90000 read, 48507 write accesses @688615500
-system.cpu7: completed 90000 read, 48310 write accesses @688789000
-system.cpu0: completed 90000 read, 48650 write accesses @689991000
-system.cpu1: completed 90000 read, 48621 write accesses @693117500
-system.cpu3: completed 90000 read, 48493 write accesses @697608000
-system.cpu5: completed 90000 read, 49008 write accesses @701381500
-system.cpu6: completed 100000 read, 53851 write accesses @761435500
-hack: be nice to actually delete the event here
+++ /dev/null
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:12
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 761435500 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000653 # Number of seconds simulated
-sim_ticks 652606500 # Number of ticks simulated
-final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 158104978 # Simulator tick rate (ticks/s)
-host_mem_usage 355504 # Number of bytes of host memory used
-host_seconds 4.13 # Real time elapsed on the host
-system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 79011 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 80501 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 83900 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 78451 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 80299 # Number of bytes read from this memory
-system.physmem.bytes_read::total 645272 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 398848 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5221 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5261 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5379 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5376 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5284 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5253 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5355 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5238 # Number of bytes written to this memory
-system.physmem.bytes_written::total 441215 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10966 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 11048 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10991 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11034 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11072 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 11125 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 88226 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6232 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5221 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5261 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5379 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5376 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5284 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5253 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5355 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5238 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 48599 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 122606808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 125725073 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 124189692 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 121069894 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 123353047 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 128561392 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 120211797 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 123043519 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 988761221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 611161550 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 8000227 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 8061519 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 8242333 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 8237736 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 8096763 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 8049261 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 8205557 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 8026276 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 676081222 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 611161550 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 130607035 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 133786593 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 132432025 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 129307630 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 131449809 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 136610653 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 128417354 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 131069795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1664842443 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 1664833249 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 85134 # Transaction distribution
-system.membus.trans_dist::ReadResp 85128 # Transaction distribution
-system.membus.trans_dist::WriteReq 42367 # Transaction distribution
-system.membus.trans_dist::WriteResp 42365 # Transaction distribution
-system.membus.trans_dist::Writeback 6232 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 57414 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution
-system.membus.trans_dist::ReadExReq 48586 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3092 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 417062 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 417062 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1086481 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 1086481 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 1086481 # Total data (bytes)
-system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 43.9 # Layer utilization (%)
-system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 47.7 # Layer utilization (%)
-system.l2c.tags.replacements 13254 # number of replacements
-system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use
-system.l2c.tags.total_refs 149317 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy
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-system.l2c.ReadReq_hits::cpu3 10808 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4 10723 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5 10748 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6 10725 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7 10838 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 85773 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 74336 # number of Writeback hits
-system.l2c.Writeback_hits::total 74336 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 332 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 322 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 337 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 354 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 332 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 353 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 349 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 378 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2757 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu3 1850 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1871 # number of ReadExReq hits
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-system.l2c.ReadExReq_hits::cpu6 1953 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1858 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 14999 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu2 12612 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3 12658 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4 12594 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 12557 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 12678 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 12696 # number of demand (read+write) hits
-system.l2c.demand_hits::total 100772 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu2 12612 # number of overall hits
-system.l2c.overall_hits::cpu3 12658 # number of overall hits
-system.l2c.overall_hits::cpu4 12594 # number of overall hits
-system.l2c.overall_hits::cpu5 12557 # number of overall hits
-system.l2c.overall_hits::cpu6 12678 # number of overall hits
-system.l2c.overall_hits::cpu7 12696 # number of overall hits
-system.l2c.overall_hits::total 100772 # number of overall hits
-system.l2c.ReadReq_misses::cpu0 751 # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu2 744 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3 696 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4 727 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5 735 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6 708 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7 698 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 5801 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0 1964 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1 1929 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2 1920 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3 1880 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 1830 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 1887 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 1921 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 1963 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 15294 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0 4321 # number of ReadExReq misses
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-system.l2c.ReadExReq_misses::cpu2 4358 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3 4233 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4 4361 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5 4404 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6 4224 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7 4317 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 34571 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0 5072 # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu2 5102 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3 4929 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4 5088 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5 5139 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6 4932 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7 5015 # number of demand (read+write) misses
-system.l2c.demand_misses::total 40372 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0 5072 # number of overall misses
-system.l2c.overall_misses::cpu1 5095 # number of overall misses
-system.l2c.overall_misses::cpu2 5102 # number of overall misses
-system.l2c.overall_misses::cpu3 4929 # number of overall misses
-system.l2c.overall_misses::cpu4 5088 # number of overall misses
-system.l2c.overall_misses::cpu5 5139 # number of overall misses
-system.l2c.overall_misses::cpu6 4932 # number of overall misses
-system.l2c.overall_misses::cpu7 5015 # number of overall misses
-system.l2c.overall_misses::total 40372 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0 46656500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1 45888000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2 46214500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3 43225999 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu4 45481000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu5 44732500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu6 43604500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu7 43142000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 358944999 # number of ReadReq miss cycles
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-system.l2c.UpgradeReq_miss_latency::cpu1 56107500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2 54698000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3 55749000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu4 51718500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu5 55828000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6 55452500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7 58605500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 442641000 # number of UpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::cpu1 234531000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2 234959000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3 228552499 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu4 234872500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu5 237965000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu6 227719000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu7 232651999 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 1863605497 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0 279010999 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1 280419000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2 281173500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3 271778498 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu4 280353500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5 282697500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu6 271323500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu7 275793999 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 2222550496 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0 279010999 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1 280419000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2 281173500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3 271778498 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu4 280353500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5 282697500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6 271323500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7 275793999 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 2222550496 # number of overall miss cycles
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-system.l2c.ReadReq_accesses::cpu2 11488 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3 11504 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu4 11450 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu5 11483 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu6 11433 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu7 11536 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 91574 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 74336 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 74336 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0 2296 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1 2251 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2 2257 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3 2234 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4 2162 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5 2240 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6 2270 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7 2341 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 18051 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::cpu2 6226 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3 6083 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu4 6232 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu5 6213 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu6 6177 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu7 6175 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 49570 # number of ReadExReq accesses(hits+misses)
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-system.l2c.demand_accesses::cpu3 17587 # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu5 17696 # number of demand (read+write) accesses
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-system.l2c.overall_accesses::total 141144 # number of overall (read+write) accesses
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-system.l2c.ReadReq_miss_rate::cpu3 0.060501 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu4 0.063493 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu5 0.064008 # miss rate for ReadReq accesses
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-system.l2c.ReadReq_miss_rate::cpu7 0.060506 # miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu1 0.856952 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2 0.850687 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3 0.841540 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.846438 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5 0.842411 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6 0.846256 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7 0.838531 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.847266 # miss rate for UpgradeReq accesses
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-system.l2c.ReadExReq_miss_rate::cpu2 0.699968 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3 0.695874 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu4 0.699775 # miss rate for ReadExReq accesses
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-system.l2c.ReadExReq_miss_rate::cpu6 0.683827 # miss rate for ReadExReq accesses
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-system.l2c.ReadReq_avg_miss_latency::cpu2 62116.263441 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3 62106.320402 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu4 62559.834938 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu5 60860.544218 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu6 61588.276836 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu7 61808.022923 # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu5 29585.585586 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu6 28866.475794 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu7 29855.068772 # average UpgradeReq miss latency
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-system.l2c.overall_mshr_miss_rate::cpu1 0.290398 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2 0.287400 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3 0.279923 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4 0.287128 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5 0.289840 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6 0.279557 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7 0.282706 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.285503 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50241.610738 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50083.559783 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 50166.665224 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50647.711512 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48672.366621 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49487.197724 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49793.650794 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 49887.074183 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41010.443199 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41083.462934 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41056.510417 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41096.327834 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41046.994536 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41059.088500 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41058.042686 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40995.160469 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41050.385823 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41681.565308 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41767.586207 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41819.058553 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41891.843735 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41772.956841 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41953.387904 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41820.023697 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41810.848169 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41814.683912 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 42941.141418 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 42956.136900 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 43033.287374 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu6 42914.889295 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 42915.717795 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 42967.739435 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 42941.141418 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 42956.136900 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 43033.287374 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 42914.889295 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 42915.717795 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 42967.739435 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.funcbus.throughput 0 # Throughput (bytes/s)
-system.funcbus.data_through_bus 0 # Total data (bytes)
-system.toL2Bus.throughput 51078499831 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 368070 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 368059 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 42367 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 42365 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 74336 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 28719 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118285 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 118639 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 118896 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119078 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118813 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 118602 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 118904 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119137 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 950354 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1731443 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1726092 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1741657 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1748194 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742487 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1735937 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741406 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1745057 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 13912273 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 13912273 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 157373515 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 158243013 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 157858027 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 24.2 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 157862988 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 24.2 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 158148657 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 24.2 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 157838676 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 24.2 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 158178516 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 24.2 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 157763244 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 24.2 # Layer utilization (%)
-system.cpu0.num_reads 98977 # number of read accesses completed
-system.cpu0.num_writes 53590 # number of write accesses completed
-system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.l1c.tags.replacements 21970 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks.
-system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy
-system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1118 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9803 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9803 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9803 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9803 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 35704 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 35704 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23289 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23289 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 58993 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 58993 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 58993 # number of overall misses
-system.cpu0.l1c.overall_misses::total 58993 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 937059642 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 937059642 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 866806760 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 866806760 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 1803866402 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 1803866402 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 1803866402 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 1803866402 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 44389 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 44389 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 24407 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 24407 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 68796 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 68796 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 68796 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 68796 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804343 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.804343 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954193 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.954193 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.857506 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.857506 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.857506 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.857506 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26245.228602 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 26245.228602 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37219.578342 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 37219.578342 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 30577.634669 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 30577.634669 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 30577.634669 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 30577.634669 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 1018391 # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 62068 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.407666 # average number of cycles each access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.l1c.fast_writes 0 # number of fast writes performed
-system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9494 # number of writebacks
-system.cpu0.l1c.writebacks::total 9494 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35704 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 35704 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23289 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 23289 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 58993 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 58993 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 58993 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 58993 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 860700776 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 860700776 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 817560778 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 817560778 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1678261554 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 1678261554 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1678261554 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 1678261554 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 703193894 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 703193894 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1636775658 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1636775658 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2339969552 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2339969552 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804343 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804343 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954193 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954193 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857506 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.857506 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857506 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.857506 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24106.564419 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24106.564419 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 35105.018592 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 35105.018592 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28448.486329 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28448.486329 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28448.486329 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28448.486329 # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 99824 # number of read accesses completed
-system.cpu1.num_writes 53636 # number of write accesses completed
-system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.l1c.tags.replacements 22223 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 395.298418 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13436 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22630 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.593725 # Average number of references to valid blocks.
-system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 395.298418 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.772067 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.772067 # Average percentage of cache occupancy
-system.cpu1.l1c.ReadReq_hits::cpu1 8757 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8757 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1135 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1135 # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1 9892 # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total 9892 # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1 9892 # number of overall hits
-system.cpu1.l1c.overall_hits::total 9892 # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1 36260 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total 36260 # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1 23033 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total 23033 # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1 59293 # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total 59293 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 59293 # number of overall misses
-system.cpu1.l1c.overall_misses::total 59293 # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1 947629716 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total 947629716 # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1 858813201 # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total 858813201 # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency::cpu1 1806442917 # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_latency::total 1806442917 # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1 1806442917 # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total 1806442917 # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1 45017 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total 45017 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1 24168 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total 24168 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1 69185 # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total 69185 # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1 69185 # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total 69185 # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805473 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total 0.805473 # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953037 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total 0.953037 # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1 0.857021 # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total 0.857021 # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1 0.857021 # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total 0.857021 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26134.299945 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 26134.299945 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 37286.206790 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 37286.206790 # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 30466.377431 # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 30466.377431 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 30466.377431 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 30466.377431 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 1020302 # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 62395 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.352304 # average number of cycles each access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.l1c.fast_writes 0 # number of fast writes performed
-system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9512 # number of writebacks
-system.cpu1.l1c.writebacks::total 9512 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36260 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36260 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23033 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 59293 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 59293 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 59293 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 59293 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 870111848 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 870111848 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 810087173 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 810087173 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1680199021 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 1680199021 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1680199021 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1680199021 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 702431869 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 702431869 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1631991143 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1631991143 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2334423012 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2334423012 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805473 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805473 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953037 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953037 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857021 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.857021 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857021 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.857021 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23996.465747 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23996.465747 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35170.719099 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 35170.719099 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.223972 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.223972 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.223972 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.223972 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 99336 # number of read accesses completed
-system.cpu2.num_writes 53403 # number of write accesses completed
-system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.l1c.tags.replacements 22214 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 394.859577 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13307 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.588441 # Average number of references to valid blocks.
-system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 394.859577 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.771210 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.771210 # Average percentage of cache occupancy
-system.cpu2.l1c.ReadReq_hits::cpu2 8708 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8708 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1070 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1070 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9778 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9778 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9778 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9778 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36160 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36160 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 22990 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 22990 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 59150 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 59150 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 59150 # number of overall misses
-system.cpu2.l1c.overall_misses::total 59150 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 947354858 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 947354858 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 856510547 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 856510547 # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2 1803865405 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total 1803865405 # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2 1803865405 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total 1803865405 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 44868 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 44868 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 24060 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 24060 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2 68928 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total 68928 # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2 68928 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total 68928 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805920 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.805920 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955528 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.955528 # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2 0.858142 # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total 0.858142 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.858142 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.858142 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26198.972843 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 26198.972843 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37255.787168 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 37255.787168 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 30496.456551 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 30496.456551 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 30496.456551 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 30496.456551 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 1016435 # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 62092 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.369822 # average number of cycles each access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu2.l1c.fast_writes 0 # number of fast writes performed
-system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9582 # number of writebacks
-system.cpu2.l1c.writebacks::total 9582 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36160 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36160 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22990 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 22990 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 59150 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 59150 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 59150 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 59150 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 870067956 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 870067956 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 807866531 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 807866531 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1677934487 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 1677934487 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1677934487 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1677934487 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 699720514 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 699720514 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1649553128 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1649553128 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2349273642 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2349273642 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805920 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805920 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955528 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955528 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858142 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.858142 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858142 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.858142 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24061.613827 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24061.613827 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35139.910004 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35139.910004 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28367.446948 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28367.446948 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28367.446948 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28367.446948 # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 100000 # number of read accesses completed
-system.cpu3.num_writes 53536 # number of write accesses completed
-system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.l1c.tags.replacements 22464 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 397.838914 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13424 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.587175 # Average number of references to valid blocks.
-system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 397.838914 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.777029 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.777029 # Average percentage of cache occupancy
-system.cpu3.l1c.ReadReq_hits::cpu3 8781 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8781 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1109 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1109 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9890 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9890 # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3 9890 # number of overall hits
-system.cpu3.l1c.overall_hits::total 9890 # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3 36107 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total 36107 # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3 23001 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total 23001 # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3 59108 # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total 59108 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 59108 # number of overall misses
-system.cpu3.l1c.overall_misses::total 59108 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 940989779 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 940989779 # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3 850325185 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total 850325185 # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3 1791314964 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total 1791314964 # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3 1791314964 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total 1791314964 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 44888 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 44888 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3 24110 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total 24110 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3 68998 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total 68998 # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3 68998 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total 68998 # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804380 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total 0.804380 # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954002 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total 0.954002 # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3 0.856663 # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total 0.856663 # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3 0.856663 # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total 0.856663 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26061.145457 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 26061.145457 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 36969.052867 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 36969.052867 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 30305.795561 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 30305.795561 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 30305.795561 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 30305.795561 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 1013074 # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 62000 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.339903 # average number of cycles each access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.l1c.fast_writes 0 # number of fast writes performed
-system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9786 # number of writebacks
-system.cpu3.l1c.writebacks::total 9786 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36107 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36107 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23001 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23001 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 59108 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 59108 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 59108 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 59108 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 863727177 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 863727177 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 801703041 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 801703041 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1665430218 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 1665430218 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1665430218 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1665430218 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 709371346 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 709371346 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1619504156 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1619504156 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2328875502 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2328875502 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804380 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804380 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954002 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954002 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856663 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.856663 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856663 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.856663 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23921.322098 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23921.322098 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34855.138516 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34855.138516 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28176.054307 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28176.054307 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28176.054307 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28176.054307 # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99830 # number of read accesses completed
-system.cpu4.num_writes 54064 # number of write accesses completed
-system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.l1c.tags.replacements 22082 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 393.544066 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13201 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22486 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.587076 # Average number of references to valid blocks.
-system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 393.544066 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.768641 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.768641 # Average percentage of cache occupancy
-system.cpu4.l1c.ReadReq_hits::cpu4 8712 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8712 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1102 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total 1102 # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4 9814 # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total 9814 # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4 9814 # number of overall hits
-system.cpu4.l1c.overall_hits::total 9814 # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4 35977 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total 35977 # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4 23176 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total 23176 # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4 59153 # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total 59153 # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4 59153 # number of overall misses
-system.cpu4.l1c.overall_misses::total 59153 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 943945635 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 943945635 # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4 856485364 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total 856485364 # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4 1800430999 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total 1800430999 # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4 1800430999 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total 1800430999 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 44689 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total 44689 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4 24278 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total 24278 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4 68967 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total 68967 # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4 68967 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total 68967 # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805053 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total 0.805053 # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954609 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total 0.954609 # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4 0.857700 # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total 0.857700 # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4 0.857700 # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total 0.857700 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26237.474915 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 26237.474915 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 36955.702623 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 36955.702623 # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 30436.850185 # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 30436.850185 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 30436.850185 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 30436.850185 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 1017670 # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 62294 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.336565 # average number of cycles each access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu4.l1c.fast_writes 0 # number of fast writes performed
-system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks 9622 # number of writebacks
-system.cpu4.l1c.writebacks::total 9622 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35977 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 35977 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23176 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 23176 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 59153 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 59153 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 59153 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 59153 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 867154515 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 867154515 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 807437346 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 807437346 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1674591861 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 1674591861 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1674591861 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 1674591861 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 707224870 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 707224870 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1620907679 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1620907679 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2328132549 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2328132549 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805053 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805053 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954609 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954609 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857700 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total 0.857700 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857700 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.857700 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24103.024571 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24103.024571 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34839.374612 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34839.374612 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28309.500127 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28309.500127 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28309.500127 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28309.500127 # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 99630 # number of read accesses completed
-system.cpu5.num_writes 53500 # number of write accesses completed
-system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.l1c.tags.replacements 22051 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 395.592742 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13484 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22450 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.600624 # Average number of references to valid blocks.
-system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 395.592742 # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5 0.772642 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total 0.772642 # Average percentage of cache occupancy
-system.cpu5.l1c.ReadReq_hits::cpu5 8824 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8824 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1160 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total 1160 # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5 9984 # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total 9984 # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5 9984 # number of overall hits
-system.cpu5.l1c.overall_hits::total 9984 # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5 36108 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total 36108 # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5 23031 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total 23031 # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5 59139 # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total 59139 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 59139 # number of overall misses
-system.cpu5.l1c.overall_misses::total 59139 # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5 948980493 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total 948980493 # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5 861190152 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total 861190152 # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5 1810170645 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total 1810170645 # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5 1810170645 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total 1810170645 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 44932 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total 44932 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5 24191 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total 24191 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5 69123 # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total 69123 # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5 69123 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total 69123 # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.803614 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total 0.803614 # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952048 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total 0.952048 # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5 0.855562 # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total 0.855562 # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5 0.855562 # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total 0.855562 # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26281.724078 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 26281.724078 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37392.651296 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 37392.651296 # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 30608.746259 # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 30608.746259 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 30608.746259 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 30608.746259 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 1024769 # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 62427 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.415477 # average number of cycles each access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu5.l1c.fast_writes 0 # number of fast writes performed
-system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9521 # number of writebacks
-system.cpu5.l1c.writebacks::total 9521 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36108 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36108 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23031 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 23031 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 59139 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 59139 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 59139 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 59139 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 871850549 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 871850549 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 812508000 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 812508000 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1684358549 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total 1684358549 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1684358549 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 1684358549 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 704255884 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 704255884 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1614286606 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1614286606 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2318542490 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2318542490 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.803614 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.803614 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952048 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952048 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.855562 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.855562 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.855562 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.855562 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24145.633904 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24145.633904 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35278.884981 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35278.884981 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28481.349854 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28481.349854 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28481.349854 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28481.349854 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.num_reads 99897 # number of read accesses completed
-system.cpu6.num_writes 53584 # number of write accesses completed
-system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.l1c.tags.replacements 22385 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks.
-system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6 395.582005 # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6 0.772621 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total 0.772621 # Average percentage of cache occupancy
-system.cpu6.l1c.ReadReq_hits::cpu6 8715 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8715 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1094 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total 1094 # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6 9809 # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total 9809 # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6 9809 # number of overall hits
-system.cpu6.l1c.overall_hits::total 9809 # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6 36235 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total 36235 # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6 23035 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total 23035 # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6 59270 # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total 59270 # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6 59270 # number of overall misses
-system.cpu6.l1c.overall_misses::total 59270 # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6 950668375 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total 950668375 # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6 850880053 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total 850880053 # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6 1801548428 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total 1801548428 # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6 1801548428 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total 1801548428 # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6 44950 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total 44950 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6 24129 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total 24129 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6 69079 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total 69079 # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6 69079 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total 69079 # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806118 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total 0.806118 # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954660 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total 0.954660 # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6 0.858003 # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total 0.858003 # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6 0.858003 # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total 0.858003 # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26236.190838 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 26236.190838 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36938.574040 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 36938.574040 # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 30395.620516 # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 30395.620516 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 30395.620516 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 30395.620516 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 1011987 # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 61933 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.340029 # average number of cycles each access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu6.l1c.fast_writes 0 # number of fast writes performed
-system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9690 # number of writebacks
-system.cpu6.l1c.writebacks::total 9690 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36235 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36235 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23035 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 23035 # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6 59270 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total 59270 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6 59270 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total 59270 # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 873220563 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 873220563 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 802141037 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 802141037 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1675361600 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total 1675361600 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1675361600 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 1675361600 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 697661939 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 697661939 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1639994129 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1639994129 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2337656068 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2337656068 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806118 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806118 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954660 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954660 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.858003 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.858003 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24098.815041 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24098.815041 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34822.706186 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34822.706186 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 99207 # number of read accesses completed
-system.cpu7.num_writes 53401 # number of write accesses completed
-system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.l1c.tags.replacements 22143 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks.
-system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy
-system.cpu7.l1c.ReadReq_hits::cpu7 8635 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8635 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7 1078 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total 1078 # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7 9713 # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total 9713 # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7 9713 # number of overall hits
-system.cpu7.l1c.overall_hits::total 9713 # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7 36141 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total 36141 # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7 23098 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total 23098 # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7 59239 # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total 59239 # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7 59239 # number of overall misses
-system.cpu7.l1c.overall_misses::total 59239 # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7 942615817 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total 942615817 # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7 859348059 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total 859348059 # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7 1801963876 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total 1801963876 # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7 1801963876 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total 1801963876 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7 44776 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total 44776 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7 24176 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total 24176 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7 68952 # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7 68952 # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807151 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total 0.807151 # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955410 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total 0.955410 # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7 0.859134 # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total 0.859134 # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7 0.859134 # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total 0.859134 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26081.619684 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 26081.619684 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37204.435839 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 37204.435839 # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 30418.539746 # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 30418.539746 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 30418.539746 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 30418.539746 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 1024987 # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 62690 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.350088 # average number of cycles each access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu7.l1c.fast_writes 0 # number of fast writes performed
-system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks 9629 # number of writebacks
-system.cpu7.l1c.writebacks::total 9629 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36141 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36141 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23098 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total 23098 # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7 59239 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total 59239 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7 59239 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total 59239 # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 865505701 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 865505701 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 810567819 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 810567819 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1676073520 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total 1676073520 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1676073520 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 1676073520 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 711693302 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 711693302 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1603062205 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1603062205 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2314755507 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2314755507 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807151 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807151 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955410 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955410 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.859134 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.859134 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23948.028582 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23948.028582 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35092.554290 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35092.554290 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem l2c membus physmem toL2Bus
+boot_osflags=a
+clock=1000
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=timing
+mem_ranges=
+memories=system.funcmem system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.cpu0]
+type=MemTest
+children=l1c
+atomic=false
+clock=500
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[0]
+test=system.cpu0.l1c.cpu_side
+
+[system.cpu0.l1c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.test
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu1]
+type=MemTest
+children=l1c
+atomic=false
+clock=500
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[1]
+test=system.cpu1.l1c.cpu_side
+
+[system.cpu1.l1c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.test
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu2]
+type=MemTest
+children=l1c
+atomic=false
+clock=500
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[2]
+test=system.cpu2.l1c.cpu_side
+
+[system.cpu2.l1c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.test
+mem_side=system.toL2Bus.slave[2]
+
+[system.cpu3]
+type=MemTest
+children=l1c
+atomic=false
+clock=500
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[3]
+test=system.cpu3.l1c.cpu_side
+
+[system.cpu3.l1c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.test
+mem_side=system.toL2Bus.slave[3]
+
+[system.cpu4]
+type=MemTest
+children=l1c
+atomic=false
+clock=500
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[4]
+test=system.cpu4.l1c.cpu_side
+
+[system.cpu4.l1c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu4.test
+mem_side=system.toL2Bus.slave[4]
+
+[system.cpu5]
+type=MemTest
+children=l1c
+atomic=false
+clock=500
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[5]
+test=system.cpu5.l1c.cpu_side
+
+[system.cpu5.l1c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu5.test
+mem_side=system.toL2Bus.slave[5]
+
+[system.cpu6]
+type=MemTest
+children=l1c
+atomic=false
+clock=500
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[6]
+test=system.cpu6.l1c.cpu_side
+
+[system.cpu6.l1c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu6.test
+mem_side=system.toL2Bus.slave[6]
+
+[system.cpu7]
+type=MemTest
+children=l1c
+atomic=false
+clock=500
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[7]
+test=system.cpu7.l1c.cpu_side
+
+[system.cpu7.l1c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=4
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+size=32768
+system=system
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu7.test
+mem_side=system.toL2Bus.slave[7]
+
+[system.funcbus]
+type=NoncoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+use_default_range=false
+width=8
+master=system.funcmem.port
+slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.funcmem]
+type=SimpleMemory
+bandwidth=73.000000
+clock=1000
+conf_table_reported=false
+in_addr_map=false
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.funcbus.master[0]
+
+[system.l2c]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=65536
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
+
+[system.membus]
+type=CoherentBus
+block_size=64
+clock=1000
+header_cycles=1
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.l2c.mem_side system.system_port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clock=1000
+conf_table_reported=false
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.master[0]
+
+[system.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+system=system
+use_default_range=false
+width=16
+master=system.l2c.cpu_side
+slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
+
--- /dev/null
+system.cpu6: completed 10000 read, 5435 write accesses @79021500
+system.cpu0: completed 10000 read, 5363 write accesses @79194500
+system.cpu7: completed 10000 read, 5392 write accesses @79770500
+system.cpu2: completed 10000 read, 5375 write accesses @80689500
+system.cpu1: completed 10000 read, 5373 write accesses @81623500
+system.cpu4: completed 10000 read, 5458 write accesses @81916000
+system.cpu5: completed 10000 read, 5507 write accesses @81975000
+system.cpu3: completed 10000 read, 5421 write accesses @82381000
+system.cpu2: completed 20000 read, 10678 write accesses @153864500
+system.cpu0: completed 20000 read, 10854 write accesses @154789000
+system.cpu7: completed 20000 read, 10817 write accesses @154953500
+system.cpu1: completed 20000 read, 10781 write accesses @155855500
+system.cpu3: completed 20000 read, 10799 write accesses @157033000
+system.cpu4: completed 20000 read, 10854 write accesses @157158000
+system.cpu6: completed 20000 read, 10878 write accesses @157795000
+system.cpu5: completed 20000 read, 10963 write accesses @159866500
+system.cpu0: completed 30000 read, 16180 write accesses @228385000
+system.cpu2: completed 30000 read, 15995 write accesses @229109500
+system.cpu7: completed 30000 read, 16232 write accesses @231170000
+system.cpu1: completed 30000 read, 16165 write accesses @231658500
+system.cpu4: completed 30000 read, 16252 write accesses @232783000
+system.cpu6: completed 30000 read, 16228 write accesses @233712000
+system.cpu3: completed 30000 read, 16226 write accesses @236523000
+system.cpu5: completed 30000 read, 16456 write accesses @239602000
+system.cpu0: completed 40000 read, 21598 write accesses @305262000
+system.cpu2: completed 40000 read, 21332 write accesses @306571000
+system.cpu1: completed 40000 read, 21599 write accesses @307778500
+system.cpu4: completed 40000 read, 21599 write accesses @307971000
+system.cpu7: completed 40000 read, 21551 write accesses @308441000
+system.cpu6: completed 40000 read, 21597 write accesses @310397000
+system.cpu3: completed 40000 read, 21704 write accesses @312891000
+system.cpu5: completed 40000 read, 21914 write accesses @315565000
+system.cpu4: completed 50000 read, 26891 write accesses @381925000
+system.cpu0: completed 50000 read, 26990 write accesses @382095500
+system.cpu2: completed 50000 read, 26686 write accesses @382917500
+system.cpu1: completed 50000 read, 26983 write accesses @384289000
+system.cpu6: completed 50000 read, 27066 write accesses @384539000
+system.cpu7: completed 50000 read, 26943 write accesses @385136500
+system.cpu3: completed 50000 read, 27037 write accesses @389922000
+system.cpu5: completed 50000 read, 27423 write accesses @393691500
+system.cpu6: completed 60000 read, 32353 write accesses @457634500
+system.cpu4: completed 60000 read, 32228 write accesses @457992000
+system.cpu1: completed 60000 read, 32457 write accesses @460714000
+system.cpu2: completed 60000 read, 32178 write accesses @461196500
+system.cpu0: completed 60000 read, 32542 write accesses @461690000
+system.cpu7: completed 60000 read, 32302 write accesses @462388500
+system.cpu3: completed 60000 read, 32488 write accesses @466103000
+system.cpu5: completed 60000 read, 32744 write accesses @469778000
+system.cpu6: completed 70000 read, 37747 write accesses @533745000
+system.cpu2: completed 70000 read, 37532 write accesses @535320500
+system.cpu4: completed 70000 read, 37773 write accesses @535591500
+system.cpu7: completed 70000 read, 37639 write accesses @538124500
+system.cpu0: completed 70000 read, 37909 write accesses @538334500
+system.cpu1: completed 70000 read, 37921 write accesses @541231500
+system.cpu3: completed 70000 read, 37871 write accesses @542226500
+system.cpu5: completed 70000 read, 38229 write accesses @548322500
+system.cpu4: completed 80000 read, 42983 write accesses @610769500
+system.cpu6: completed 80000 read, 43020 write accesses @610776000
+system.cpu2: completed 80000 read, 42982 write accesses @611661000
+system.cpu0: completed 80000 read, 43374 write accesses @615085500
+system.cpu1: completed 80000 read, 43250 write accesses @615627500
+system.cpu7: completed 80000 read, 43033 write accesses @615746000
+system.cpu3: completed 80000 read, 43154 write accesses @619760000
+system.cpu5: completed 80000 read, 43738 write accesses @625688001
+system.cpu6: completed 90000 read, 48339 write accesses @685422000
+system.cpu2: completed 90000 read, 48272 write accesses @687608500
+system.cpu4: completed 90000 read, 48507 write accesses @688615500
+system.cpu7: completed 90000 read, 48310 write accesses @688789000
+system.cpu0: completed 90000 read, 48650 write accesses @689991000
+system.cpu1: completed 90000 read, 48621 write accesses @693117500
+system.cpu3: completed 90000 read, 48493 write accesses @697608000
+system.cpu5: completed 90000 read, 49008 write accesses @701381500
+system.cpu6: completed 100000 read, 53851 write accesses @761435500
+hack: be nice to actually delete the event here
--- /dev/null
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Mar 26 2013 14:38:52
+gem5 started Mar 26 2013 14:39:12
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 761435500 because maximum number of loads reached
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000653 # Number of seconds simulated
+sim_ticks 652606500 # Number of ticks simulated
+final_tick 652606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_tick_rate 158104978 # Simulator tick rate (ticks/s)
+host_mem_usage 355504 # Number of bytes of host memory used
+host_seconds 4.13 # Real time elapsed on the host
+system.physmem.bytes_read::cpu0 80014 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 82049 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 81047 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 79011 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 80501 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 83900 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 78451 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 80299 # Number of bytes read from this memory
+system.physmem.bytes_read::total 645272 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 398848 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5221 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5261 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5379 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5376 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5284 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5253 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5355 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5238 # Number of bytes written to this memory
+system.physmem.bytes_written::total 441215 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 10966 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 11048 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10991 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 11034 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11072 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 11125 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 88226 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6232 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5221 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5261 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5379 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5376 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5284 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5253 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5355 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5238 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 48599 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 122606808 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 125725073 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 124189692 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 121069894 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 123353047 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 128561392 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 120211797 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 123043519 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 988761221 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 611161550 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 8000227 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 8061519 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 8242333 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 8237736 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 8096763 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 8049261 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 8205557 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 8026276 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 676081222 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 611161550 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 130607035 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 133786593 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 132432025 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 129307630 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 131449809 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 136610653 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 128417354 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 131069795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1664842443 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 1664833249 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 85134 # Transaction distribution
+system.membus.trans_dist::ReadResp 85128 # Transaction distribution
+system.membus.trans_dist::WriteReq 42367 # Transaction distribution
+system.membus.trans_dist::WriteResp 42365 # Transaction distribution
+system.membus.trans_dist::Writeback 6232 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 57414 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 46744 # Transaction distribution
+system.membus.trans_dist::ReadExReq 48586 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3092 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 417062 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 417062 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1086481 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 1086481 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1086481 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 286485584 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 43.9 # Layer utilization (%)
+system.membus.respLayer0.occupancy 311361500 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 47.7 # Layer utilization (%)
+system.l2c.tags.replacements 13254 # number of replacements
+system.l2c.tags.tagsinuse 783.820018 # Cycle average of tags in use
+system.l2c.tags.total_refs 149317 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 14065 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 10.616210 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 726.472153 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0 7.679894 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1 7.566050 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2 7.311161 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3 6.856177 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4 7.195523 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5 6.988954 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6 6.739476 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7 7.010629 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.709445 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0 0.007500 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1 0.007389 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2 0.007140 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4 0.007027 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5 0.006825 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6 0.006582 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7 0.006846 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.765449 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0 10635 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1 10552 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2 10744 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3 10808 # number of ReadReq hits
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+system.l2c.ReadReq_hits::total 85773 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 74336 # number of Writeback hits
+system.l2c.Writeback_hits::total 74336 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0 332 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1 322 # number of UpgradeReq hits
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+system.l2c.UpgradeReq_hits::cpu3 354 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4 332 # number of UpgradeReq hits
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+system.l2c.UpgradeReq_hits::cpu6 349 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7 378 # number of UpgradeReq hits
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+system.l2c.overall_mshr_uncacheable_latency::total 5072344000 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0 0.065431 # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu5 0.063659 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6 0.061489 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060073 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.062856 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854965 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.856952 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.850687 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.841092 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.846438 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.842411 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.846256 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838531 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.847155 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690769 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.700145 # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.695381 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.698973 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.707871 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.683180 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.698623 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.696813 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.287067 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.290398 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.287400 # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::cpu4 0.287128 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.289840 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.279557 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.282706 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.285503 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.287067 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.290398 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.287400 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.279923 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu6 0.279557 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::total 0.285503 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50241.610738 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50000 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48672.366621 # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41010.443199 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41083.462934 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41056.510417 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41096.327834 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41046.994536 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41059.088500 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41058.042686 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40995.160469 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41050.385823 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41681.565308 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41767.586207 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41819.058553 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41891.843735 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41772.956841 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41953.387904 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41820.023697 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41810.848169 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41814.683912 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 42941.141418 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 42956.136900 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 43033.287374 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu7 42915.717795 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 42967.739435 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu2 43013.847967 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 43056.672354 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.996296 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 42914.889295 # average overall mshr miss latency
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.funcbus.throughput 0 # Throughput (bytes/s)
+system.funcbus.data_through_bus 0 # Total data (bytes)
+system.toL2Bus.throughput 51078499831 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 368070 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 368059 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 42367 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 42365 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 74336 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 28719 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 28718 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 155928 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 155926 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118285 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 118639 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 118896 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119078 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118813 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 118602 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 118904 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119137 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 950354 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1731443 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1726092 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1741657 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1748194 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742487 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1735937 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1741406 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1745057 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 13912273 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 13912273 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 19421888 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 652560490 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 157373515 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 158243013 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 157858027 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 24.2 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 157862988 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 24.2 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 158148657 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 24.2 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 157838676 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 24.2 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 158178516 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 24.2 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 157763244 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 24.2 # Layer utilization (%)
+system.cpu0.num_reads 98977 # number of read accesses completed
+system.cpu0.num_writes 53590 # number of write accesses completed
+system.cpu0.num_copies 0 # number of copy accesses completed
+system.cpu0.l1c.tags.replacements 21970 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 393.709596 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13350 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22370 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.596781 # Average number of references to valid blocks.
+system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.l1c.tags.occ_blocks::cpu0 393.709596 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.768964 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.768964 # Average percentage of cache occupancy
+system.cpu0.l1c.ReadReq_hits::cpu0 8685 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8685 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1118 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1118 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 9803 # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total 9803 # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0 9803 # number of overall hits
+system.cpu0.l1c.overall_hits::total 9803 # number of overall hits
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+system.cpu1.l1c.overall_avg_miss_latency::cpu1 30466.377431 # average overall miss latency
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+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23996.465747 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23996.465747 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 35170.719099 # average WriteReq mshr miss latency
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+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
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+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu2.l1c.tags.sampled_refs 22614 # Sample count of references to valid blocks.
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+system.cpu2.l1c.ReadReq_misses::total 36160 # number of ReadReq misses
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+system.cpu2.l1c.WriteReq_misses::total 22990 # number of WriteReq misses
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+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23921.322098 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23921.322098 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34855.138516 # average WriteReq mshr miss latency
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+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu4.l1c.ReadReq_misses::total 35977 # number of ReadReq misses
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+system.cpu4.l1c.ReadReq_avg_miss_latency::total 26237.474915 # average ReadReq miss latency
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+system.cpu4.l1c.WriteReq_avg_miss_latency::total 36955.702623 # average WriteReq miss latency
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+system.cpu4.l1c.demand_avg_miss_latency::total 30436.850185 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 30436.850185 # average overall miss latency
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+system.cpu4.l1c.demand_mshr_miss_latency::total 1674591861 # number of demand (read+write) MSHR miss cycles
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+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu5.l1c.overall_miss_latency::total 1810170645 # number of overall miss cycles
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+system.cpu5.l1c.ReadReq_avg_miss_latency::total 26281.724078 # average ReadReq miss latency
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+system.cpu5.l1c.WriteReq_avg_miss_latency::total 37392.651296 # average WriteReq miss latency
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+system.cpu5.l1c.demand_avg_miss_latency::total 30608.746259 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 30608.746259 # average overall miss latency
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+system.cpu5.l1c.overall_mshr_miss_rate::total 0.855562 # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24145.633904 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24145.633904 # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35278.884981 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35278.884981 # average WriteReq mshr miss latency
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+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28481.349854 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28481.349854 # average overall mshr miss latency
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+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu6.num_writes 53584 # number of write accesses completed
+system.cpu6.num_copies 0 # number of copy accesses completed
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+system.cpu6.l1c.tags.tagsinuse 395.582005 # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs 13337 # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs 0.585136 # Average number of references to valid blocks.
+system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu6.l1c.overall_hits::total 9809 # number of overall hits
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+system.cpu6.l1c.ReadReq_misses::total 36235 # number of ReadReq misses
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+system.cpu6.l1c.WriteReq_misses::total 23035 # number of WriteReq misses
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+system.cpu6.l1c.demand_misses::total 59270 # number of demand (read+write) misses
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+system.cpu6.l1c.overall_misses::total 59270 # number of overall misses
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+system.cpu6.l1c.ReadReq_miss_latency::total 950668375 # number of ReadReq miss cycles
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+system.cpu6.l1c.overall_miss_latency::total 1801548428 # number of overall miss cycles
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+system.cpu6.l1c.overall_accesses::total 69079 # number of overall (read+write) accesses
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+system.cpu6.l1c.overall_miss_rate::total 0.858003 # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26236.190838 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 26236.190838 # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36938.574040 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 36938.574040 # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 30395.620516 # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 30395.620516 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 30395.620516 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 30395.620516 # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs 1011987 # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs 61933 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.340029 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu6.l1c.fast_writes 0 # number of fast writes performed
+system.cpu6.l1c.cache_copies 0 # number of cache copies performed
+system.cpu6.l1c.writebacks::writebacks 9690 # number of writebacks
+system.cpu6.l1c.writebacks::total 9690 # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36235 # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total 36235 # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23035 # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total 23035 # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6 59270 # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total 59270 # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6 59270 # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total 59270 # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 873220563 # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total 873220563 # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 802141037 # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total 802141037 # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1675361600 # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total 1675361600 # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1675361600 # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total 1675361600 # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 697661939 # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 697661939 # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1639994129 # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1639994129 # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2337656068 # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2337656068 # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806118 # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806118 # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954660 # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954660 # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_miss_rate::total 0.858003 # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858003 # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total 0.858003 # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24098.815041 # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24098.815041 # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34822.706186 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34822.706186 # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28266.603678 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28266.603678 # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu7.num_reads 99207 # number of read accesses completed
+system.cpu7.num_writes 53401 # number of write accesses completed
+system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu7.l1c.tags.replacements 22143 # number of replacements
+system.cpu7.l1c.tags.tagsinuse 394.587693 # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs 13403 # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs 22544 # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs 0.594526 # Average number of references to valid blocks.
+system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu7.l1c.tags.occ_blocks::cpu7 394.587693 # Average occupied blocks per requestor
+system.cpu7.l1c.tags.occ_percent::cpu7 0.770679 # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_percent::total 0.770679 # Average percentage of cache occupancy
+system.cpu7.l1c.ReadReq_hits::cpu7 8635 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total 8635 # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7 1078 # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total 1078 # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7 9713 # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total 9713 # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7 9713 # number of overall hits
+system.cpu7.l1c.overall_hits::total 9713 # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7 36141 # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total 36141 # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7 23098 # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total 23098 # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7 59239 # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total 59239 # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7 59239 # number of overall misses
+system.cpu7.l1c.overall_misses::total 59239 # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7 942615817 # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total 942615817 # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7 859348059 # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total 859348059 # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7 1801963876 # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total 1801963876 # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7 1801963876 # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total 1801963876 # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7 44776 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total 44776 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7 24176 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total 24176 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7 68952 # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7 68952 # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807151 # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_miss_rate::total 0.807151 # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955410 # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::total 0.955410 # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7 0.859134 # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total 0.859134 # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7 0.859134 # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total 0.859134 # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26081.619684 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 26081.619684 # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37204.435839 # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 37204.435839 # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 30418.539746 # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 30418.539746 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 30418.539746 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 30418.539746 # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs 1024987 # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs 62690 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.350088 # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu7.l1c.fast_writes 0 # number of fast writes performed
+system.cpu7.l1c.cache_copies 0 # number of cache copies performed
+system.cpu7.l1c.writebacks::writebacks 9629 # number of writebacks
+system.cpu7.l1c.writebacks::total 9629 # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36141 # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total 36141 # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23098 # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total 23098 # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7 59239 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total 59239 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7 59239 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total 59239 # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 865505701 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total 865505701 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 810567819 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total 810567819 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1676073520 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total 1676073520 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1676073520 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total 1676073520 # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 711693302 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 711693302 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1603062205 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1603062205 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2314755507 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2314755507 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807151 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807151 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955410 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955410 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total 0.859134 # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859134 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total 0.859134 # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23948.028582 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23948.028582 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35092.554290 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35092.554290 # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28293.413461 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28293.413461 # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-hack: be nice to actually delete the event here
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Aug 6 2012 15:52:45
-gem5 started Aug 6 2012 15:56:03
-gem5 executing on 61f1f4j
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 300940000 because Done
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.100000 # Number of seconds simulated
-sim_ticks 100000000000 # Number of ticks simulated
-final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 12102739985 # Simulator tick rate (ticks/s)
-host_mem_usage 228608 # Number of bytes of host memory used
-host_seconds 8.26 # Real time elapsed on the host
-system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
-system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory
-system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3333299 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu 2133311360 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller
-system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
-system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
-system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
-system.physmem.bytesRead 213331136 # Total number of bytes read from memory
-system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
-system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 217600 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 217600 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 210100 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 99999960000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 3333300 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 3301421 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 26232 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 1073 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 946 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 938 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 802 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 538 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 402 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 540 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 270 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 138 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 26100 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 8168.810421 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 8140.398372 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 356.874580 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65 16 0.06% 0.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393 99 0.38% 0.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193 25985 99.56% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 26100 # Bytes accessed per row activation
-system.physmem.totQLat 1278758950 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 63884930200 # Sum of mem lat for all requests
-system.physmem.totBusLat 16666500000 # Total cycles spent in databus access
-system.physmem.totBankLat 45939671250 # Total cycles spent in bank access
-system.physmem.avgQLat 383.63 # Average queueing delay per request
-system.physmem.avgBankLat 13782.04 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 19165.67 # Average memory access latency
-system.physmem.avgRdBW 2133.31 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2133.31 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 16.67 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.64 # Average read queue length over time
-system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 3307200 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.22 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 30000.29 # Average gap between requests
-system.membus.throughput 2133311360 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 3333300 # Transaction distribution
-system.membus.trans_dist::ReadResp 3333299 # Transaction distribution
-system.membus.pkt_count_system.monitor-master::system.physmem.port 6666599 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6666599 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213331136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 213331136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 213331136 # Total data (bytes)
-system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 6.3 # Layer utilization (%)
-system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 17.2 # Layer utilization (%)
-system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::24-27 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::28-31 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::32-35 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::36-39 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::40-43 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::44-47 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::64-67 3333300 100.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::total 3333300 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::samples 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::mean nan # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::gmean nan # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::stdev nan # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::0 0 # Histogram of burst lengths of transmitted packets
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-system.monitor.writeBurstLengthHist::5 0 # Histogram of burst lengths of transmitted packets
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-system.monitor.writeBurstLengthHist::8 0 # Histogram of burst lengths of transmitted packets
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-system.monitor.writeBurstLengthHist::11 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::12 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::13 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::14 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::15 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::16 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::17 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::18 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::19 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets
-system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean 2133311359.990499 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev 6399.944145 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::4.02653e+08-5.36871e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::5.36871e+08-6.71089e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::6.71089e+08-8.05306e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::8.05306e+08-9.39524e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::9.39524e+08-1.07374e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.07374e+09-1.20796e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.20796e+09-1.34218e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.34218e+09-1.4764e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.4764e+09-1.61061e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.61061e+09-1.74483e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.74483e+09-1.87905e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::1.87905e+09-2.01327e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.01327e+09-2.14748e+09 100 100.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.14748e+09-2.2817e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.2817e+09-2.41592e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::total 100 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.averageReadBandwidth 2133311360 0.00% 0.00% # Average read bandwidth (bytes/s)
-system.monitor.totalReadBytes 213331136 # Number of bytes read
-system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::mean 0 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::gmean 0 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::stdev 0 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::0 100 100.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::3 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::4 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::5 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::6 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::7 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::8 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::9 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::10 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::11 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::12 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::13 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::14 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::15 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::16 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::17 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::18 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::19 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s)
-system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s)
-system.monitor.totalWrittenBytes 0 # Number of bytes written
-system.monitor.readLatencyHist::samples 3333299 # Read request-response latency
-system.monitor.readLatencyHist::mean 39172.137513 # Read request-response latency
-system.monitor.readLatencyHist::gmean 38967.643311 # Read request-response latency
-system.monitor.readLatencyHist::stdev 6823.352873 # Read request-response latency
-system.monitor.readLatencyHist::0-32767 12686 0.38% 0.38% # Read request-response latency
-system.monitor.readLatencyHist::32768-65535 3289137 98.68% 99.06% # Read request-response latency
-system.monitor.readLatencyHist::65536-98303 26638 0.80% 99.85% # Read request-response latency
-system.monitor.readLatencyHist::98304-131071 937 0.03% 99.88% # Read request-response latency
-system.monitor.readLatencyHist::131072-163839 1073 0.03% 99.92% # Read request-response latency
-system.monitor.readLatencyHist::163840-196607 808 0.02% 99.94% # Read request-response latency
-system.monitor.readLatencyHist::196608-229375 670 0.02% 99.96% # Read request-response latency
-system.monitor.readLatencyHist::229376-262143 670 0.02% 99.98% # Read request-response latency
-system.monitor.readLatencyHist::262144-294911 272 0.01% 99.99% # Read request-response latency
-system.monitor.readLatencyHist::294912-327679 270 0.01% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::327680-360447 138 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::458752-491519 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::491520-524287 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::524288-557055 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::total 3333299 # Read request-response latency
-system.monitor.writeLatencyHist::samples 0 # Write request-response latency
-system.monitor.writeLatencyHist::mean nan # Write request-response latency
-system.monitor.writeLatencyHist::gmean nan # Write request-response latency
-system.monitor.writeLatencyHist::stdev nan # Write request-response latency
-system.monitor.writeLatencyHist::0 0 # Write request-response latency
-system.monitor.writeLatencyHist::1 0 # Write request-response latency
-system.monitor.writeLatencyHist::2 0 # Write request-response latency
-system.monitor.writeLatencyHist::3 0 # Write request-response latency
-system.monitor.writeLatencyHist::4 0 # Write request-response latency
-system.monitor.writeLatencyHist::5 0 # Write request-response latency
-system.monitor.writeLatencyHist::6 0 # Write request-response latency
-system.monitor.writeLatencyHist::7 0 # Write request-response latency
-system.monitor.writeLatencyHist::8 0 # Write request-response latency
-system.monitor.writeLatencyHist::9 0 # Write request-response latency
-system.monitor.writeLatencyHist::10 0 # Write request-response latency
-system.monitor.writeLatencyHist::11 0 # Write request-response latency
-system.monitor.writeLatencyHist::12 0 # Write request-response latency
-system.monitor.writeLatencyHist::13 0 # Write request-response latency
-system.monitor.writeLatencyHist::14 0 # Write request-response latency
-system.monitor.writeLatencyHist::15 0 # Write request-response latency
-system.monitor.writeLatencyHist::16 0 # Write request-response latency
-system.monitor.writeLatencyHist::17 0 # Write request-response latency
-system.monitor.writeLatencyHist::18 0 # Write request-response latency
-system.monitor.writeLatencyHist::19 0 # Write request-response latency
-system.monitor.writeLatencyHist::total 0 # Write request-response latency
-system.monitor.ittReadRead::samples 3333299 # Read-to-read inter transaction time
-system.monitor.ittReadRead::mean 30000.297003 # Read-to-read inter transaction time
-system.monitor.ittReadRead::stdev 54.497186 # Read-to-read inter transaction time
-system.monitor.ittReadRead::underflows 0 0.00% 0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::1-5000 0 0.00% 0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::5001-10000 0 0.00% 0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::10001-15000 0 0.00% 0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::15001-20000 0 0.00% 0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::20001-25000 0 0.00% 0.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::25001-30000 3333200 100.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::30001-35000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::35001-40000 99 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::40001-45000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::45001-50000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::50001-55000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::55001-60000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::60001-65000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::65001-70000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::70001-75000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::75001-80000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::80001-85000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::85001-90000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::90001-95000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::95001-100000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::overflows 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::min_value 30000 # Read-to-read inter transaction time
-system.monitor.ittReadRead::max_value 40000 # Read-to-read inter transaction time
-system.monitor.ittReadRead::total 3333299 # Read-to-read inter transaction time
-system.monitor.ittWriteWrite::samples 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::mean nan # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::stdev nan # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::underflows 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::1-5000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::5001-10000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::10001-15000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::15001-20000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::20001-25000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::25001-30000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::30001-35000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::35001-40000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::40001-45000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::45001-50000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::50001-55000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::55001-60000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::60001-65000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::65001-70000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::70001-75000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::75001-80000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::80001-85000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::85001-90000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::90001-95000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::95001-100000 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::overflows 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::min_value 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::max_value 0 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::total 0 # Write-to-write inter transaction time
-system.monitor.ittReqReq::samples 3333299 # Request-to-request inter transaction time
-system.monitor.ittReqReq::mean 30000.297003 # Request-to-request inter transaction time
-system.monitor.ittReqReq::stdev 54.497186 # Request-to-request inter transaction time
-system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::1-5000 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::5001-10000 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::25001-30000 3333200 100.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::35001-40000 99 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::55001-60000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::60001-65000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::65001-70000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::70001-75000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::75001-80000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::80001-85000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::overflows 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::min_value 30000 # Request-to-request inter transaction time
-system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time
-system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time
-system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean 1 # Outstanding read transactions
-system.monitor.outstandingReadsHist::gmean 1 # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev 0 # Outstanding read transactions
-system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1 100 100.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::3 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::4 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::5 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::11 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::12 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::13 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::14 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::15 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::16 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::17 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions
-system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions
-system.monitor.outstandingWritesHist::mean 0 # Outstanding write transactions
-system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions
-system.monitor.outstandingWritesHist::stdev 0 # Outstanding write transactions
-system.monitor.outstandingWritesHist::0 100 100.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::1 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::5 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::6 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::7 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::8 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::9 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::10 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::11 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::12 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::13 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::14 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::15 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::16 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::17 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::18 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions
-system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period
-system.monitor.readTransHist::mean 33333 # Histogram of read transactions per sample period
-system.monitor.readTransHist::gmean 33333.000000 # Histogram of read transactions per sample period
-system.monitor.readTransHist::stdev 0 # Histogram of read transactions per sample period
-system.monitor.readTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::4096-6143 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::6144-8191 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::8192-10239 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::10240-12287 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::12288-14335 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::14336-16383 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::16384-18431 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::18432-20479 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::20480-22527 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::22528-24575 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::24576-26623 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::26624-28671 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::28672-30719 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::30720-32767 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::32768-34815 100 100.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::34816-36863 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::mean 0 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::gmean 0 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::stdev 0 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::0 100 100.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::1 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::2 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::3 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::4 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::5 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::6 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::7 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::8 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::9 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::10 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::11 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::12 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::13 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::14 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::15 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::16 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::17 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
-system.cpu.numPackets 3333300 # Number of packets generated
-system.cpu.numRetries 0 # Number of retries
-system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks)
-
----------- End Simulation Statistics ----------
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Aug 25 2012 13:56:00
-gem5 started Aug 25 2012 13:58:17
-gem5 executing on Andreas-MacBook-Pro.local
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 100000000000 because simulate() limit reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.100000 # Number of seconds simulated
-sim_ticks 100000000000 # Number of ticks simulated
-final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 8032030639 # Simulator tick rate (ticks/s)
-host_mem_usage 228596 # Number of bytes of host memory used
-host_seconds 12.45 # Real time elapsed on the host
-system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
-system.physmem.bytes_read::total 64 # Number of bytes read from this memory
-system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory
-system.physmem.bytes_written::total 213329152 # Number of bytes written to this memory
-system.physmem.num_reads::cpu 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu 3333268 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 3333268 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu 640 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 640 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu 2133291520 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2133291520 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu 2133292160 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2133292160 # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput 2133292160 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 1 # Transaction distribution
-system.membus.trans_dist::ReadResp 1 # Transaction distribution
-system.membus.trans_dist::WriteReq 3333268 # Transaction distribution
-system.membus.trans_dist::WriteResp 3333267 # Transaction distribution
-system.membus.pkt_count_system.monitor-master::system.physmem.port 6666537 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6666537 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 213329216 # Total data (bytes)
-system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 16.7 # Layer utilization (%)
-system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 3.3 # Layer utilization (%)
-system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::stdev nan # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::24-27 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::28-31 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::32-35 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::36-39 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::40-43 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::44-47 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::64-67 1 100.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::total 1 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::samples 3333268 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::24-27 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::28-31 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::32-35 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::36-39 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::40-43 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::44-47 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::48-51 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::64-67 3333268 100.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::total 3333268 # Histogram of burst lengths of transmitted packets
-system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::mean 640 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean 0 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev 6400 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::0-4095 99 99.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::4096-8191 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::8192-12287 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::12288-16383 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::16384-20479 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::20480-24575 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::24576-28671 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::28672-32767 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::32768-36863 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::36864-40959 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::40960-45055 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::45056-49151 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::49152-53247 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::53248-57343 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::57344-61439 0 0.00% 99.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::61440-65535 1 1.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::65536-69631 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::69632-73727 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::73728-77823 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::77824-81919 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::total 100 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.averageReadBandwidth 640 0.00% 0.00% # Average read bandwidth (bytes/s)
-system.monitor.totalReadBytes 64 # Number of bytes read
-system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::mean 2133291520 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::gmean 2133291510.261604 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::stdev 204800 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::4.02653e+08-5.36871e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::5.36871e+08-6.71089e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::6.71089e+08-8.05306e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::8.05306e+08-9.39524e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::9.39524e+08-1.07374e+09 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.07374e+09-1.20796e+09 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.20796e+09-1.34218e+09 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.34218e+09-1.4764e+09 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.4764e+09-1.61061e+09 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.61061e+09-1.74483e+09 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.74483e+09-1.87905e+09 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::1.87905e+09-2.01327e+09 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.01327e+09-2.14748e+09 100 100.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.14748e+09-2.2817e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.2817e+09-2.41592e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s)
-system.monitor.averageWriteBandwidth 2133291520 0.00% 0.00% # Average write bandwidth (bytes/s)
-system.monitor.totalWrittenBytes 213329152 # Number of bytes written
-system.monitor.readLatencyHist::samples 1 # Read request-response latency
-system.monitor.readLatencyHist::mean 30000 # Read request-response latency
-system.monitor.readLatencyHist::gmean 30000.000000 # Read request-response latency
-system.monitor.readLatencyHist::stdev nan # Read request-response latency
-system.monitor.readLatencyHist::0-2047 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::2048-4095 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::4096-6143 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::6144-8191 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::8192-10239 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::10240-12287 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::12288-14335 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::14336-16383 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::16384-18431 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::18432-20479 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::20480-22527 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::22528-24575 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::24576-26623 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::26624-28671 0 0.00% 0.00% # Read request-response latency
-system.monitor.readLatencyHist::28672-30719 1 100.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::30720-32767 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::32768-34815 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::34816-36863 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::total 1 # Read request-response latency
-system.monitor.writeLatencyHist::samples 3333267 # Write request-response latency
-system.monitor.writeLatencyHist::mean 30000.000098 # Write request-response latency
-system.monitor.writeLatencyHist::gmean 30000.000081 # Write request-response latency
-system.monitor.writeLatencyHist::stdev 0.179655 # Write request-response latency
-system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::6144-8191 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::8192-10239 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::10240-12287 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::12288-14335 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::14336-16383 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::16384-18431 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::18432-20479 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::20480-22527 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::22528-24575 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::24576-26623 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::26624-28671 0 0.00% 0.00% # Write request-response latency
-system.monitor.writeLatencyHist::28672-30719 3333267 100.00% 100.00% # Write request-response latency
-system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency
-system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency
-system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency
-system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency
-system.monitor.writeLatencyHist::38912-40959 0 0.00% 100.00% # Write request-response latency
-system.monitor.writeLatencyHist::total 3333267 # Write request-response latency
-system.monitor.ittReadRead::samples 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::mean nan # Read-to-read inter transaction time
-system.monitor.ittReadRead::stdev nan # Read-to-read inter transaction time
-system.monitor.ittReadRead::underflows 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::1-5000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::5001-10000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::10001-15000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::15001-20000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::20001-25000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::25001-30000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::30001-35000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::35001-40000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::40001-45000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::45001-50000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::50001-55000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::55001-60000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::60001-65000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::65001-70000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::70001-75000 0 # Read-to-read inter transaction time
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-system.monitor.ittReadRead::80001-85000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::85001-90000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::90001-95000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::95001-100000 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::overflows 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::min_value 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::max_value 0 # Read-to-read inter transaction time
-system.monitor.ittReadRead::total 0 # Read-to-read inter transaction time
-system.monitor.ittWriteWrite::samples 3333267 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::mean 30000.595310 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::stdev 547.340980 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::5001-10000 0 0.00% 0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::10001-15000 0 0.00% 0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::15001-20000 0 0.00% 0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::20001-25000 0 0.00% 0.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::25001-30000 3333167 100.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::30001-35000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::35001-40000 99 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::40001-45000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::45001-50000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::50001-55000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::55001-60000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::60001-65000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::65001-70000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::70001-75000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::75001-80000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::80001-85000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::85001-90000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::90001-95000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::95001-100000 0 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::overflows 1 0.00% 100.00% # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::min_value 30000 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::max_value 1024328 # Write-to-write inter transaction time
-system.monitor.ittWriteWrite::total 3333267 # Write-to-write inter transaction time
-system.monitor.ittReqReq::samples 3333268 # Request-to-request inter transaction time
-system.monitor.ittReqReq::mean 30000.587712 # Request-to-request inter transaction time
-system.monitor.ittReqReq::stdev 547.516688 # Request-to-request inter transaction time
-system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::1-5000 1 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::5001-10000 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::25001-30000 3333167 100.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::35001-40000 99 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time
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-system.monitor.ittReqReq::60001-65000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::65001-70000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::70001-75000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::75001-80000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::80001-85000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::min_value 4672 # Request-to-request inter transaction time
-system.monitor.ittReqReq::max_value 1024328 # Request-to-request inter transaction time
-system.monitor.ittReqReq::total 3333268 # Request-to-request inter transaction time
-system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean 0 # Outstanding read transactions
-system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev 0 # Outstanding read transactions
-system.monitor.outstandingReadsHist::0 100 100.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::3 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::4 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::5 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::11 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::12 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::13 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::14 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::15 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::16 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::17 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions
-system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions
-system.monitor.outstandingWritesHist::mean 1 # Outstanding write transactions
-system.monitor.outstandingWritesHist::gmean 1 # Outstanding write transactions
-system.monitor.outstandingWritesHist::stdev 0 # Outstanding write transactions
-system.monitor.outstandingWritesHist::0 0 0.00% 0.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::1 100 100.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::5 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::6 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::7 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::8 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::9 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::10 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::11 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::12 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::13 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::14 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::15 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::16 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::17 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::18 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions
-system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions
-system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period
-system.monitor.readTransHist::mean 0.010000 # Histogram of read transactions per sample period
-system.monitor.readTransHist::gmean 0 # Histogram of read transactions per sample period
-system.monitor.readTransHist::stdev 0.100000 # Histogram of read transactions per sample period
-system.monitor.readTransHist::0 99 99.00% 99.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::1 1 1.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::2 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::3 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::4 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::5 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::6 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::7 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::8 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::9 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::10 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::11 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::12 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::13 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::14 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::15 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::16 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::17 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::mean 33332.680000 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::gmean 33332.679848 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::stdev 3.200000 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::4096-6143 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::6144-8191 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::8192-10239 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::10240-12287 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::12288-14335 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::14336-16383 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::16384-18431 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::18432-20479 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::20480-22527 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::22528-24575 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::24576-26623 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::26624-28671 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::28672-30719 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::30720-32767 0 0.00% 0.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::32768-34815 100 100.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period
-system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
-system.cpu.numPackets 3333269 # Number of packets generated
-system.cpu.numRetries 1 # Number of retries
-system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks)
-
----------- End Simulation Statistics ----------
--- /dev/null
+hack: be nice to actually delete the event here
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Aug 6 2012 15:52:45
+gem5 started Aug 6 2012 15:56:03
+gem5 executing on 61f1f4j
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 300940000 because Done
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.100000 # Number of seconds simulated
+sim_ticks 100000000000 # Number of ticks simulated
+final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_tick_rate 12102739985 # Simulator tick rate (ticks/s)
+host_mem_usage 228608 # Number of bytes of host memory used
+host_seconds 8.26 # Real time elapsed on the host
+system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
+system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory
+system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3333299 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu 2133311360 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 3333300 # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts 3333300 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
+system.physmem.bytesRead 213331136 # Total number of bytes read from memory
+system.physmem.bytesWritten 0 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
+system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 217600 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 217600 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 210100 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
+system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 99999960000 # Total gap between requests
+system.physmem.readPktSize::0 0 # Categorize read packet sizes
+system.physmem.readPktSize::1 0 # Categorize read packet sizes
+system.physmem.readPktSize::2 0 # Categorize read packet sizes
+system.physmem.readPktSize::3 0 # Categorize read packet sizes
+system.physmem.readPktSize::4 0 # Categorize read packet sizes
+system.physmem.readPktSize::5 0 # Categorize read packet sizes
+system.physmem.readPktSize::6 3333300 # Categorize read packet sizes
+system.physmem.writePktSize::0 0 # Categorize write packet sizes
+system.physmem.writePktSize::1 0 # Categorize write packet sizes
+system.physmem.writePktSize::2 0 # Categorize write packet sizes
+system.physmem.writePktSize::3 0 # Categorize write packet sizes
+system.physmem.writePktSize::4 0 # Categorize write packet sizes
+system.physmem.writePktSize::5 0 # Categorize write packet sizes
+system.physmem.writePktSize::6 0 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 3301421 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 26232 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1073 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 946 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 938 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 802 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 538 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 402 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 540 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 270 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 138 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 26100 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 8168.810421 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 8140.398372 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 356.874580 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 16 0.06% 0.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 99 0.38% 0.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 25985 99.56% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 26100 # Bytes accessed per row activation
+system.physmem.totQLat 1278758950 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 63884930200 # Sum of mem lat for all requests
+system.physmem.totBusLat 16666500000 # Total cycles spent in databus access
+system.physmem.totBankLat 45939671250 # Total cycles spent in bank access
+system.physmem.avgQLat 383.63 # Average queueing delay per request
+system.physmem.avgBankLat 13782.04 # Average bank access latency per request
+system.physmem.avgBusLat 5000.00 # Average bus latency per request
+system.physmem.avgMemAccLat 19165.67 # Average memory access latency
+system.physmem.avgRdBW 2133.31 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2133.31 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
+system.physmem.busUtil 16.67 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.64 # Average read queue length over time
+system.physmem.avgWrQLen 0.00 # Average write queue length over time
+system.physmem.readRowHits 3307200 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.22 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap 30000.29 # Average gap between requests
+system.membus.throughput 2133311360 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3333300 # Transaction distribution
+system.membus.trans_dist::ReadResp 3333299 # Transaction distribution
+system.membus.pkt_count_system.monitor-master::system.physmem.port 6666599 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6666599 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213331136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 213331136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 213331136 # Total data (bytes)
+system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 6.3 # Layer utilization (%)
+system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 17.2 # Layer utilization (%)
+system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::24-27 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::28-31 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::32-35 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::36-39 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::40-43 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::44-47 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::48-51 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::64-67 3333300 100.00% 100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::total 3333300 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::samples 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::mean nan # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::gmean nan # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::stdev nan # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::0 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::1 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::2 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::3 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::4 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::5 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::6 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::7 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::8 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::9 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::10 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::11 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::12 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::13 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::14 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::15 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::16 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::17 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::18 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::19 0 # Histogram of burst lengths of transmitted packets
+system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets
+system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::gmean 2133311359.990499 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::stdev 6399.944145 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::4.02653e+08-5.36871e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::5.36871e+08-6.71089e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::6.71089e+08-8.05306e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::8.05306e+08-9.39524e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::9.39524e+08-1.07374e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.07374e+09-1.20796e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.20796e+09-1.34218e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.34218e+09-1.4764e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.4764e+09-1.61061e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.61061e+09-1.74483e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.74483e+09-1.87905e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::1.87905e+09-2.01327e+09 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::2.01327e+09-2.14748e+09 100 100.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::2.14748e+09-2.2817e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::2.2817e+09-2.41592e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::total 100 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.averageReadBandwidth 2133311360 0.00% 0.00% # Average read bandwidth (bytes/s)
+system.monitor.totalReadBytes 213331136 # Number of bytes read
+system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::mean 0 # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::gmean 0 # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::stdev 0 # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::0 100 100.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::1 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::2 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::3 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::4 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::5 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::6 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::7 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::8 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::9 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::10 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::11 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::12 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::13 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::14 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::15 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::16 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::17 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::18 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::19 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s)
+system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s)
+system.monitor.totalWrittenBytes 0 # Number of bytes written
+system.monitor.readLatencyHist::samples 3333299 # Read request-response latency
+system.monitor.readLatencyHist::mean 39172.137513 # Read request-response latency
+system.monitor.readLatencyHist::gmean 38967.643311 # Read request-response latency
+system.monitor.readLatencyHist::stdev 6823.352873 # Read request-response latency
+system.monitor.readLatencyHist::0-32767 12686 0.38% 0.38% # Read request-response latency
+system.monitor.readLatencyHist::32768-65535 3289137 98.68% 99.06% # Read request-response latency
+system.monitor.readLatencyHist::65536-98303 26638 0.80% 99.85% # Read request-response latency
+system.monitor.readLatencyHist::98304-131071 937 0.03% 99.88% # Read request-response latency
+system.monitor.readLatencyHist::131072-163839 1073 0.03% 99.92% # Read request-response latency
+system.monitor.readLatencyHist::163840-196607 808 0.02% 99.94% # Read request-response latency
+system.monitor.readLatencyHist::196608-229375 670 0.02% 99.96% # Read request-response latency
+system.monitor.readLatencyHist::229376-262143 670 0.02% 99.98% # Read request-response latency
+system.monitor.readLatencyHist::262144-294911 272 0.01% 99.99% # Read request-response latency
+system.monitor.readLatencyHist::294912-327679 270 0.01% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::327680-360447 138 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency
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+system.monitor.readLatencyHist::491520-524287 0 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::524288-557055 0 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::total 3333299 # Read request-response latency
+system.monitor.writeLatencyHist::samples 0 # Write request-response latency
+system.monitor.writeLatencyHist::mean nan # Write request-response latency
+system.monitor.writeLatencyHist::gmean nan # Write request-response latency
+system.monitor.writeLatencyHist::stdev nan # Write request-response latency
+system.monitor.writeLatencyHist::0 0 # Write request-response latency
+system.monitor.writeLatencyHist::1 0 # Write request-response latency
+system.monitor.writeLatencyHist::2 0 # Write request-response latency
+system.monitor.writeLatencyHist::3 0 # Write request-response latency
+system.monitor.writeLatencyHist::4 0 # Write request-response latency
+system.monitor.writeLatencyHist::5 0 # Write request-response latency
+system.monitor.writeLatencyHist::6 0 # Write request-response latency
+system.monitor.writeLatencyHist::7 0 # Write request-response latency
+system.monitor.writeLatencyHist::8 0 # Write request-response latency
+system.monitor.writeLatencyHist::9 0 # Write request-response latency
+system.monitor.writeLatencyHist::10 0 # Write request-response latency
+system.monitor.writeLatencyHist::11 0 # Write request-response latency
+system.monitor.writeLatencyHist::12 0 # Write request-response latency
+system.monitor.writeLatencyHist::13 0 # Write request-response latency
+system.monitor.writeLatencyHist::14 0 # Write request-response latency
+system.monitor.writeLatencyHist::15 0 # Write request-response latency
+system.monitor.writeLatencyHist::16 0 # Write request-response latency
+system.monitor.writeLatencyHist::17 0 # Write request-response latency
+system.monitor.writeLatencyHist::18 0 # Write request-response latency
+system.monitor.writeLatencyHist::19 0 # Write request-response latency
+system.monitor.writeLatencyHist::total 0 # Write request-response latency
+system.monitor.ittReadRead::samples 3333299 # Read-to-read inter transaction time
+system.monitor.ittReadRead::mean 30000.297003 # Read-to-read inter transaction time
+system.monitor.ittReadRead::stdev 54.497186 # Read-to-read inter transaction time
+system.monitor.ittReadRead::underflows 0 0.00% 0.00% # Read-to-read inter transaction time
+system.monitor.ittReadRead::1-5000 0 0.00% 0.00% # Read-to-read inter transaction time
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+system.monitor.ittReadRead::20001-25000 0 0.00% 0.00% # Read-to-read inter transaction time
+system.monitor.ittReadRead::25001-30000 3333200 100.00% 100.00% # Read-to-read inter transaction time
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+system.monitor.ittReadRead::overflows 0 0.00% 100.00% # Read-to-read inter transaction time
+system.monitor.ittReadRead::min_value 30000 # Read-to-read inter transaction time
+system.monitor.ittReadRead::max_value 40000 # Read-to-read inter transaction time
+system.monitor.ittReadRead::total 3333299 # Read-to-read inter transaction time
+system.monitor.ittWriteWrite::samples 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::mean nan # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::stdev nan # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::underflows 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::1-5000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::5001-10000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::10001-15000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::15001-20000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::20001-25000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::25001-30000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::30001-35000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::35001-40000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::40001-45000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::45001-50000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::50001-55000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::55001-60000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::60001-65000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::65001-70000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::70001-75000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::75001-80000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::80001-85000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::85001-90000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::90001-95000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::95001-100000 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::overflows 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::min_value 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::max_value 0 # Write-to-write inter transaction time
+system.monitor.ittWriteWrite::total 0 # Write-to-write inter transaction time
+system.monitor.ittReqReq::samples 3333299 # Request-to-request inter transaction time
+system.monitor.ittReqReq::mean 30000.297003 # Request-to-request inter transaction time
+system.monitor.ittReqReq::stdev 54.497186 # Request-to-request inter transaction time
+system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::1-5000 0 0.00% 0.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::5001-10000 0 0.00% 0.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::25001-30000 3333200 100.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time
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+system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time
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+system.monitor.ittReqReq::60001-65000 0 0.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::65001-70000 0 0.00% 100.00% # Request-to-request inter transaction time
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+system.monitor.ittReqReq::75001-80000 0 0.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::80001-85000 0 0.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::overflows 0 0.00% 100.00% # Request-to-request inter transaction time
+system.monitor.ittReqReq::min_value 30000 # Request-to-request inter transaction time
+system.monitor.ittReqReq::max_value 40000 # Request-to-request inter transaction time
+system.monitor.ittReqReq::total 3333299 # Request-to-request inter transaction time
+system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
+system.monitor.outstandingReadsHist::mean 1 # Outstanding read transactions
+system.monitor.outstandingReadsHist::gmean 1 # Outstanding read transactions
+system.monitor.outstandingReadsHist::stdev 0 # Outstanding read transactions
+system.monitor.outstandingReadsHist::0 0 0.00% 0.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::1 100 100.00% 100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::2 0 0.00% 100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::3 0 0.00% 100.00% # Outstanding read transactions
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+system.monitor.outstandingReadsHist::5 0 0.00% 100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions
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+system.monitor.outstandingReadsHist::12 0 0.00% 100.00% # Outstanding read transactions
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+system.monitor.outstandingReadsHist::14 0 0.00% 100.00% # Outstanding read transactions
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+system.monitor.outstandingReadsHist::16 0 0.00% 100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::17 0 0.00% 100.00% # Outstanding read transactions
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+system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions
+system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions
+system.monitor.outstandingWritesHist::mean 0 # Outstanding write transactions
+system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions
+system.monitor.outstandingWritesHist::stdev 0 # Outstanding write transactions
+system.monitor.outstandingWritesHist::0 100 100.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::1 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::5 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::6 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::7 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::8 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::9 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::10 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::11 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::12 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::13 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::14 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::15 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::16 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::17 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::18 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions
+system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period
+system.monitor.readTransHist::mean 33333 # Histogram of read transactions per sample period
+system.monitor.readTransHist::gmean 33333.000000 # Histogram of read transactions per sample period
+system.monitor.readTransHist::stdev 0 # Histogram of read transactions per sample period
+system.monitor.readTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::4096-6143 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::6144-8191 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::8192-10239 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::10240-12287 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::12288-14335 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::14336-16383 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::16384-18431 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::18432-20479 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::20480-22527 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::22528-24575 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::24576-26623 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::26624-28671 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::28672-30719 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::30720-32767 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::32768-34815 100 100.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::34816-36863 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::mean 0 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::gmean 0 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::stdev 0 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::0 100 100.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::1 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::2 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::3 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::4 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::5 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::6 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::7 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::8 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::9 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::10 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::11 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::12 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::13 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::14 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::15 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::16 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::17 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
+system.cpu.numPackets 3333300 # Number of packets generated
+system.cpu.numRetries 0 # Number of retries
+system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks)
+
+---------- End Simulation Statistics ----------
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Aug 25 2012 13:56:00
+gem5 started Aug 25 2012 13:58:17
+gem5 executing on Andreas-MacBook-Pro.local
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 100000000000 because simulate() limit reached
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.100000 # Number of seconds simulated
+sim_ticks 100000000000 # Number of ticks simulated
+final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_tick_rate 8032030639 # Simulator tick rate (ticks/s)
+host_mem_usage 228596 # Number of bytes of host memory used
+host_seconds 12.45 # Real time elapsed on the host
+system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
+system.physmem.bytes_read::total 64 # Number of bytes read from this memory
+system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory
+system.physmem.bytes_written::total 213329152 # Number of bytes written to this memory
+system.physmem.num_reads::cpu 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu 3333268 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 3333268 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu 640 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 640 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu 2133291520 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2133291520 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu 2133292160 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2133292160 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 2133292160 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1 # Transaction distribution
+system.membus.trans_dist::ReadResp 1 # Transaction distribution
+system.membus.trans_dist::WriteReq 3333268 # Transaction distribution
+system.membus.trans_dist::WriteResp 3333267 # Transaction distribution
+system.membus.pkt_count_system.monitor-master::system.physmem.port 6666537 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6666537 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.monitor-master::system.physmem.port 213329216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 213329216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 213329216 # Total data (bytes)
+system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 16.7 # Layer utilization (%)
+system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 3.3 # Layer utilization (%)
+system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::stdev nan # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::24-27 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::28-31 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
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+system.monitor.outstandingWritesHist::1 100 100.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::5 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::6 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::7 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::8 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::9 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::10 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::11 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::12 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::13 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::14 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::15 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::16 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::17 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::18 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions
+system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions
+system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period
+system.monitor.readTransHist::mean 0.010000 # Histogram of read transactions per sample period
+system.monitor.readTransHist::gmean 0 # Histogram of read transactions per sample period
+system.monitor.readTransHist::stdev 0.100000 # Histogram of read transactions per sample period
+system.monitor.readTransHist::0 99 99.00% 99.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::1 1 1.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::2 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::3 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::4 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::5 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::6 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::7 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::8 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::9 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::10 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::11 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::12 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::13 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::14 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::15 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::16 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::17 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::mean 33332.680000 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::gmean 33332.679848 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::stdev 3.200000 # Histogram of read transactions per sample period
+system.monitor.writeTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::4096-6143 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::6144-8191 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::8192-10239 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::10240-12287 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::12288-14335 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::14336-16383 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::16384-18431 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::18432-20479 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::20480-22527 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::22528-24575 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::24576-26623 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::26624-28671 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::28672-30719 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::30720-32767 0 0.00% 0.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::32768-34815 100 100.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period
+system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period
+system.cpu.numPackets 3333269 # Number of packets generated
+system.cpu.numRetries 1 # Number of retries
+system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks)
+
+---------- End Simulation Statistics ----------
def initCPU(cpu):
# We might actually have a MemTest object or something similar
# here that just pretends to be a CPU.
- if isinstance(cpu, BaseCPU):
+ try:
cpu.createThreads()
+ except:
+ pass
# The CPU attribute doesn't exist in some cases, e.g. the Ruby
# testers.
projects / gem5.git / commitdiff