+++ /dev/null
-TARGET_ISA = 'no'
-CPU_MODELS = 'no'
--- /dev/null
+TARGET_ISA = 'null'
+CPU_MODELS = ''
Import('*')
+if env['TARGET_ISA'] == 'null':
+ Return()
+
Source('decode_cache.cc')
+++ /dev/null
-
-Import('*')
-
-all_isa_list.append('no')
+++ /dev/null
-
-class BaseCPU
-{
- public:
- static int numSimulatedInsts() { return 0; }
- static int numSimulatedOps() { return 0; }
-};
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+Import('*')
+
+if env['TARGET_ISA'] == 'null':
+ Source('cpu_dummy.cc')
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+Import('*')
+
+all_isa_list.append('null')
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+/**
+ * Provide the actual storage for maxThreadsPerCPU which is declared
+ * extern and normally provided by src/cpu/base.cc
+ */
+int maxThreadsPerCPU = 1;
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#ifndef __ARCH_NULL_CPU_DUMMY_HH__
+#define __ARCH_NULL_CPU_DUMMY_HH__
+
+#include "sim/core.hh"
+
+class BaseCPU
+{
+ public:
+ static int numSimulatedInsts() { return 0; }
+ static int numSimulatedOps() { return 0; }
+};
+
+#endif // __ARCH_NULL_CPU_DUMMY_HH__
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#ifndef __ARCH_NULL_ISA_TRAITS_HH__
+#define __ARCH_NULL_ISA_TRAITS_HH__
+
+#include "base/types.hh"
+
+namespace LittleEndianGuest {}
+
+namespace NullISA
+{
+ using namespace LittleEndianGuest;
+
+ const Addr PageShift = 12;
+ const Addr PageBytes = ULL(1) << PageShift;
+
+ const int LogVMPageSize = 12; // 4K bytes
+ const int VMPageSize = (1 << LogVMPageSize);
+
+}
+
+#endif //__ARCH_NULL_ISA_TRAITS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#ifndef __ARCH_NULL_REGISTERS_HH__
+#define __ARCH_NULL_REGISTERS_HH__
+
+#include "base/types.hh"
+
+namespace NullISA {
+
+typedef uint64_t IntReg;
+typedef uint32_t FloatRegBits;
+typedef float FloatReg;
+typedef uint64_t MiscReg;
+
+}
+
+#endif // __ARCH_NULL_REGISTERS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#ifndef __ARCH_NULL_REMOTE_GDB_HH__
+#define __ARCH_NULL_REMOTE_GDB_HH__
+
+class ThreadContext;
+
+class BaseRemoteGDB
+{
+
+ public:
+
+ bool breakpoint() { return false; }
+ void replaceThreadContext(ThreadContext *tc) {}
+
+ virtual ~BaseRemoteGDB() {}
+};
+
+#endif // __ARCH_NULL_REMOTE_GDB_H__
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#ifndef __ARCH_NULL_TYPES_HH__
+#define __ARCH_NULL_TYPES_HH__
+
+#include "arch/generic/types.hh"
+
+namespace NullISA
+{
+ typedef uint32_t MachInst;
+
+ class PCState : public GenericISA::UPCState<MachInst>
+ {
+ protected:
+
+ typedef GenericISA::UPCState<MachInst> Base;
+ };
+
+}
+
+#endif // __ARCH_NULL_TYPES_HH__
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#ifndef __ARCH_NULL_UTILITY_HH__
+#define __ARCH_NULL_UTILITY_HH__
+
+#include "base/types.hh"
+#include "cpu/thread_context.hh"
+
+namespace NullISA {
+
+inline uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size,
+ bool fp) { return 0; }
+
+inline void startupCPU(ThreadContext *tc, int cpuId) {}
+
+}
+
+#endif // __ARCH_NULL_UTILITY_HH__
Source('pollevent.cc')
Source('random.cc')
Source('random_mt.cc')
-if env['TARGET_ISA'] != 'no':
+if env['TARGET_ISA'] != 'null':
Source('remote_gdb.cc')
Source('socket.cc')
Source('statistics.cc')
Import('*')
-if env['TARGET_ISA'] == 'no':
+if env['TARGET_ISA'] == 'null':
+ SimObject('IntrControl.py')
+ Source('intr_control_noisa.cc')
Return()
#################################################################
#include <vector>
+// Before we do anything else, check if this build is the NULL ISA,
+// and if so stop here
+#include "config/the_isa.hh"
+#if THE_ISA == NULL_ISA
+#include "arch/null/cpu_dummy.hh"
+#else
#include "arch/interrupts.hh"
#include "arch/isa_traits.hh"
#include "arch/microcode_rom.hh"
#include "base/statistics.hh"
-#include "config/the_isa.hh"
#include "mem/mem_object.hh"
#include "sim/eventq.hh"
#include "sim/full_system.hh"
Stats::Scalar numWorkItemsCompleted;
};
+#endif // THE_ISA == NULL_ISA
+
#endif // __CPU_BASE_HH__
--- /dev/null
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Ron Dreslinski
+ */
+
+#include "cpu/intr_control.hh"
+
+using namespace std;
+
+IntrControl::IntrControl(const Params *p)
+ : SimObject(p), sys(p->sys)
+{}
+
+void
+IntrControl::post(int cpu_id, int int_num, int index)
+{
+}
+
+void
+IntrControl::clear(int cpu_id, int int_num, int index)
+{
+}
+
+IntrControl *
+IntrControlParams::create()
+{
+ return new IntrControl(this);
+}
Import('*')
-if env['TARGET_ISA'] == 'no':
+if env['TARGET_ISA'] == 'null':
Return()
SimObject('BadDevice.py')
#include <limits>
#include <string>
+#ifdef SINIC_VTOPHYS
#include "arch/vtophys.hh"
+#endif
#include "base/compiler.hh"
#include "base/debug.hh"
#include "base/inet.hh"
Import('*')
-if env['TARGET_ISA'] == 'no':
+if env['TARGET_ISA'] == 'null':
Return()
Source('kernel_stats.cc')
SimObject('CommMonitor.py')
Source('comm_monitor.cc')
+SimObject('AbstractMemory.py')
SimObject('AddrMapper.py')
SimObject('Bridge.py')
SimObject('Bus.py')
SimObject('MemObject.py')
+SimObject('SimpleMemory.py')
+SimObject('SimpleDRAM.py')
+Source('abstract_mem.cc')
Source('addr_mapper.cc')
Source('bridge.cc')
Source('bus.cc')
Source('packet_queue.cc')
Source('tport.cc')
Source('port_proxy.cc')
-Source('fs_translating_port_proxy.cc')
-Source('se_translating_port_proxy.cc')
+Source('simple_mem.cc')
+Source('physical.cc')
+Source('simple_dram.cc')
-if env['TARGET_ISA'] != 'no':
- SimObject('AbstractMemory.py')
- SimObject('SimpleMemory.py')
- SimObject('SimpleDRAM.py')
- Source('abstract_mem.cc')
- Source('simple_mem.cc')
+if env['TARGET_ISA'] != 'null':
+ Source('fs_translating_port_proxy.cc')
+ Source('se_translating_port_proxy.cc')
Source('page_table.cc')
- Source('physical.cc')
- Source('simple_dram.cc')
DebugFlag('BaseBus')
DebugFlag('BusAddrRanges')
Import('*')
-if env['TARGET_ISA'] == 'no':
- Return()
-
SimObject('BaseCache.py')
Source('base.cc')
* Definition of BaseCache functions.
*/
-#include "cpu/base.hh"
-#include "cpu/smt.hh"
#include "debug/Cache.hh"
#include "debug/Drain.hh"
#include "mem/cache/tags/fa_lru.hh"
Import('*')
-if env['TARGET_ISA'] == 'no':
- Return()
SimObject('Prefetcher.py')
Source('base.cc')
Import('*')
-if env['TARGET_ISA'] == 'no':
- Return()
-
SimObject('Tags.py')
Source('base.cc')
* Definitions of BaseTags.
*/
+#include "config/the_isa.hh"
#include "cpu/smt.hh" //maxThreadsPerCPU
#include "mem/cache/tags/base.hh"
#include "mem/cache/base.hh"
* Port object definitions.
*/
+#include "arch/vtophys.hh"
#include "base/chunk_generator.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#ifndef __MEM_FS_PORT_PROXY_HH__
#define __MEM_FS_PORT_PROXY_HH__
-#include "arch/vtophys.hh"
#include "mem/port_proxy.hh"
+class ThreadContext;
+
/**
* A TranslatingPortProxy in FS mode translates a virtual address to a
* physical address and then calls the read/write functions of the
#define __MEM_PORT_PROXY_HH__
#include "config/the_isa.hh"
-#if THE_ISA != NO_ISA
+#if THE_ISA != NULL_ISA
#include "arch/isa_traits.hh"
#endif
template <typename T>
void write(Addr address, T data) const;
-#if THE_ISA != NO_ISA
+#if THE_ISA != NULL_ISA
/**
* Read sizeof(T) bytes from address and return as object T.
* Performs Guest to Host endianness transform.
writeBlob(address, (uint8_t*)&data, sizeof(T));
}
-#if THE_ISA != NO_ISA
+#if THE_ISA != NULL_ISA
template <typename T>
T
PortProxy::readGtoH(Addr address) const
Import('*')
-if env['TARGET_ISA'] == 'no':
+if env['TARGET_ISA'] == 'null':
Return()
if env['PROTOCOL'] == 'None':
#include "base/inifile.hh"
#include "base/output.hh"
+#include "config/the_isa.hh"
+#if THE_ISA != NULL_ISA
#include "dev/etherdevice.hh"
#include "dev/etherobject.hh"
+#endif
#include "mem/mem_object.hh"
-#include "mem/port.hh"
#include "python/swig/pyobject.hh"
#include "sim/full_system.hh"
#include "sim/sim_object.hh"
using namespace std;
+#if THE_ISA != NULL_ISA
EtherInt *
lookupEthPort(SimObject *so, const std::string &name, int i)
{
p = ed->getEthPort(name, i);
return p;
}
+#endif
/**
* Connect the described MemObject ports. Called from Python via SWIG.
connectPorts(SimObject *o1, const std::string &name1, int i1,
SimObject *o2, const std::string &name2, int i2)
{
+#if THE_ISA != NULL_ISA
if (FullSystem) {
EtherObject *eo1, *eo2;
EtherDevice *ed1, *ed2;
}
}
}
+#endif
MemObject *mo1, *mo2;
mo1 = dynamic_cast<MemObject*>(o1);
mo2 = dynamic_cast<MemObject*>(o2);
SimObject('BaseTLB.py')
SimObject('ClockedObject.py')
SimObject('Root.py')
-SimObject('InstTracer.py')
SimObject('ClockDomain.py')
SimObject('VoltageDomain.py')
+SimObject('System.py')
Source('arguments.cc')
Source('async.cc')
Source('sim_object.cc')
Source('simulate.cc')
Source('stat_control.cc')
-Source('syscall_emul.cc')
Source('clock_domain.cc')
Source('voltage_domain.cc')
+Source('system.cc')
-if env['TARGET_ISA'] != 'no':
+if env['TARGET_ISA'] != 'null':
+ SimObject('InstTracer.py')
SimObject('Process.py')
- SimObject('System.py')
Source('faults.cc')
Source('process.cc')
Source('pseudo_inst.cc')
- Source('system.cc')
-
-if env['TARGET_ISA'] != 'no':
+ Source('syscall_emul.cc')
Source('tlb.cc')
DebugFlag('Checkpoint')
#include <cassert>
-#include "arch/vtophys.hh"
#include "base/refcnt.hh"
#include "base/types.hh"
#include "mem/fs_translating_port_proxy.hh"
#include "base/hostinfo.hh"
#include "base/statistics.hh"
#include "base/time.hh"
-#include "config/the_isa.hh"
-#if THE_ISA == NO_ISA
-#include "arch/noisa/cpu_dummy.hh"
-#else
#include "cpu/base.hh"
-#endif
-
#include "sim/eventq_impl.hh"
#include "sim/stat_control.hh"
#include "arch/isa_traits.hh"
#include "arch/remote_gdb.hh"
#include "arch/utility.hh"
-#include "arch/vtophys.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/str.hh"
threadContexts[id] = tc;
_numContexts++;
+#if THE_ISA != NULL_ISA
int port = getRemoteGDBPort();
if (port) {
RemoteGDB *rgdb = new RemoteGDB(this, tc);
remoteGDB[id] = rgdb;
}
+#endif
activeCpus.push_back(false);
*/
unsigned int cacheLineSize() const { return _cacheLineSize; }
+#if THE_ISA != NULL_ISA
PCEventQueue pcEventQueue;
+#endif
std::vector<ThreadContext *> threadContexts;
int _numContexts;
{
Addr addr = 0; // initialize only to avoid compiler warning
+#if THE_ISA != NULL_ISA
if (symtab->findAddress(lbl, addr)) {
T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr),
std::forward<Args>(args)...);
return ev;
}
+#endif
return NULL;
}
Import('*')
-if env['TARGET_ISA'] == 'no':
- Return()
-
Source('unittest.cc')
UnitTest('bitvectest', 'bitvectest.cc')
'ALPHA_MOESI_CMP_directory,' \
'ALPHA_MOESI_CMP_token,' \
'MIPS,' \
+ 'NULL,' \
'POWER,' \
'SPARC,' \
'X86,X86_MESI_CMP_directory,' \
projects / gem5.git / commitdiff