track down module in which vdd / vss error exists (shift)

diff --git a/experiments2/part_sig_add.py b/experiments2/part_sig_add.py
index ec7bf3b1cd1797935092757fddfc59a368ff2cfd..7c50f7650f90e549ab1407b407d2481af5b6baf5 100644 (file)
--- a/experiments2/part_sig_add.py
+++ b/experiments2/part_sig_add.py
@@ -1,5 +1,5 @@
 from nmigen.cli import rtlil
-from test_partsig import TestAddMod2
+from test_partsig import TestAddMod2, TestLS
 import subprocess
 import os
 from nmigen import Signal
@@ -7,19 +7,9 @@ from nmigen import Signal
 def test():
     width = 16
     pmask = Signal(3)  # divide into 4-bits
-    module = TestAddMod2(width, pmask)
-    sim = create_ilang(module,
-                               [pmask,
-                                module.a.sig,
-                                module.b.sig,
-                                module.add_output,
-                                module.ls_output,
-                                module.sub_output,
-                                module.carry_in,
-                                module.add_carry_out,
-                                module.sub_carry_out,
-                                module.neg_output,
-                               ],
+    #module = TestAddMod2(width, pmask)
+    module = TestLS(width, pmask)
+    sim = create_ilang(module, [pmask] + module.ports(),
                                "part_sig_add")
                             
 def create_ilang(dut, ports, test_name):

diff --git a/experiments2/test_partsig.py b/experiments2/test_partsig.py
index 3c868a4d42e29ffac4aaaccc7db985e43ba4ff28..73a63339e23d16805287378608f3d678bc4aeabf 100644 (file)
--- a/experiments2/test_partsig.py
+++ b/experiments2/test_partsig.py
@@ -10,12 +10,40 @@ from ieee754.part.partsig import PartitionedSignal
 from ieee754.part_mux.part_mux import PMux
 
 
+# XXX this is for coriolis2 experimentation
+class TestLS(Elaboratable):
+    def __init__(self, width, partpoints):
+        self.partpoints = partpoints
+        self.a = PartitionedSignal(partpoints, width, name="a")
+        self.b = PartitionedSignal(partpoints, width, name="b")
+        self.ls_output = Signal(width) # left shift
+        self.dummy_output = Signal(width) # left shift
+
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+        sync = m.d.sync
+        self.a.set_module(m)
+        self.b.set_module(m)
+        # left shift
+        sync += self.dummy_output.eq(self.b.sig) # stops sigs being ignored
+        sync += self.ls_output.eq(self.a << self.b)
+        ppts = self.partpoints
+
+        return m
+
+    def ports(self):
+        return [self.a.sig, self.b.sig,
+                self.ls_output,
+                self.dummy_output]
+
+
 # XXX this is for coriolis2 experimentation
 class TestAddMod2(Elaboratable):
     def __init__(self, width, partpoints):
         self.partpoints = partpoints
-        self.a = PartitionedSignal(partpoints, width)
-        self.b = PartitionedSignal(partpoints, width)
+        self.a = PartitionedSignal(partpoints, width, name="a")
+        self.b = PartitionedSignal(partpoints, width, name="b")
         self.add_output = Signal(width)
         self.ls_output = Signal(width) # left shift
         self.sub_output = Signal(width)
@@ -48,4 +76,14 @@ class TestAddMod2(Elaboratable):
 
         return m
 
+    def ports(self):
+        return [self.a.sig, self.b.sig,
+                self.add_output,
+                self.ls_output,
+                self.sub_output,
+                self.carry_in,
+                self.add_carry_out,
+                self.sub_carry_out,
+                self.neg_output]
+