add ClintBase
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 27 Jul 2018 09:51:40 +0000 (10:51 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 27 Jul 2018 09:51:40 +0000 (10:51 +0100)
src/core/core_parameters.bsv

index d4afdb049c46f3b53f7d0a140973f9d91b28c413..bb5811a169a39b2a559c0c01fd951b03a8c7d2c3 100644 (file)
        `define SDRAMCfgEnd  'h000117FF // 12 32-bit registers
        `define TCMBase         'h00020000 // 
        `define TCMEnd                  'h00040000 // 128KB
+    `define ClintBase       'h02000000
+    `define ClintEnd        'h020BFFFF
   `define VMEBase      'h40000000      
        `define  VMEEnd  'h4FFFFFFF // 1GB
     `ifdef FlexBus_verify