cross-reference issues under consideration

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 82d9b1d36243451d3e8bedc46687fd0f865cf928..5e8b8ff3168eec6d236a11e2231d49e7cdf61d21 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -715,7 +715,7 @@ loop:
    \item 8/16-bit ops is it worthwhile adding a "start offset"? \\
          (a bit like misaligned addressing... for registers)\\
          or just use predication to skip start?
-   \item http://libre-riscv.org/simple\_v\_extension/\#issues
+   \item see http://libre-riscv.org/simple\_v\_extension/\#issues
   \end{itemize}
 }