cross-reference issues under consideration

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 803bdba02313abd434003b79facf026cd636d4c2..4cf0937edde233618bbd012a4a8ad571c9acd473 100644 (file)
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1059,7 +1059,7 @@ Similar rules apply to the destination register.
 * Throw an exception.  Whether that actually results in spawning threads
   as part of the trap-handling remains to be seen.
 
-# Under consideration
+# Under consideration <a name="issues"></a>
 
 From the Chennai 2018 slides the following issues were raised.
 Efforts to analyse and answer these questions are below.

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 417c0f3d921824477b98097ec8ed6eb1f9a4d652..82d9b1d36243451d3e8bedc46687fd0f865cf928 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -715,6 +715,7 @@ loop:
    \item 8/16-bit ops is it worthwhile adding a "start offset"? \\
          (a bit like misaligned addressing... for registers)\\
          or just use predication to skip start?
+   \item http://libre-riscv.org/simple\_v\_extension/\#issues
   \end{itemize}
 }