def __init__(self, width):
self.width = width
self.smax = int(log(width) / log(2))
- self.i = Signal(width)
- self.s = Signal(self.smax)
- self.o = Signal(width)
+ self.i = Signal(width, reset_less=True)
+ self.s = Signal(self.smax, reset_less=True)
+ self.o = Signal(width, reset_less=True)
def elaborate(self, platform):
m = Module()
self.e_end = self.rmw + self.e_width - 3 # for decoding
self.v = Signal(width) # Latched copy of value
- self.m = Signal(m_width) # Mantissa
- self.e = Signal((e_width, True)) # Exponent: IEEE754exp+2 bits, signed
- self.s = Signal() # Sign bit
+ self.m = Signal(m_width, reset_less=True) # Mantissa
+ self.e = Signal((e_width, True), reset_less=True) # Exponent: IEEE754exp+2 bits, signed
+ self.s = Signal(reset_less=True) # Sign bit
self.mzero = Const(0, (m_width, False))
self.m1s = Const(-1, (m_width, False))
def __init__(self, width):
self.width = width
- self.v = Signal(width)
- self.stb = Signal()
- self.ack = Signal()
+ self.v = Signal(width, reset_less=True)
+ self.stb = Signal(reset_less=True)
+ self.ack = Signal(reset_less=True)
def ports(self):
return [self.v, self.stb, self.ack]
class Overflow:
def __init__(self):
- self.guard = Signal() # tot[2]
- self.round_bit = Signal() # tot[1]
- self.sticky = Signal() # tot[0]
+ self.guard = Signal(reset_less=True) # tot[2]
+ self.round_bit = Signal(reset_less=True) # tot[1]
+ self.sticky = Signal(reset_less=True) # tot[0]
class FPBase:
z = FPNum(self.width, False)
w = z.m_width + 4
- tot = Signal(w) # sticky/round/guard, {mantissa} result, 1 overflow
+ tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow
of = Overflow()
# XXX TODO: the shifter used here is quite expensive
# having only one would be better
- ediff = Signal((len(a.e), True))
- ediffr = Signal((len(a.e), True))
+ ediff = Signal((len(a.e), True), reset_less=True)
+ ediffr = Signal((len(a.e), True), reset_less=True)
m.d.comb += ediff.eq(a.e - b.e)
m.d.comb += ediffr.eq(b.e - a.e)
with m.If(ediff > 0):