remove unneeded xer.ca in MulOutputData

diff --git a/src/soc/fu/mul/pipe_data.py b/src/soc/fu/mul/pipe_data.py
index eef6cd837f1e6dd370a7de7867788fab00fcf75b..3a7abe37640f108fd26cefcbb3625d58e4fc38a5 100644 (file)
--- a/src/soc/fu/mul/pipe_data.py
+++ b/src/soc/fu/mul/pipe_data.py
@@ -16,8 +16,7 @@ class MulIntermediateData(DIVInputData):
 
 class MulOutputData(IntegerData):
     regspec = [('INT', 'o', '0:128'),
-               ('XER', 'xer_so', '32'), # XER bit 32: SO
-               ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
+               ('XER', 'xer_so', '32')] # XER bit 32: SO
     def __init__(self, pspec):
         super().__init__(pspec, False) # still input style