set upper CSns on HyperRAM to zero and set reset_n HI

fix CSn pin-pad names

diff --git a/src/ls2.py b/src/ls2.py
index c64079fe84203947210a0134022c93442142ceb2..1a2bd29bf88ab257502e6ac618946ff75acaa4dc 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -422,6 +422,7 @@ class DDR3SoC(SoC, Elaboratable):
         self.memory_map = self._decoder.bus.memory_map
 
         self.clk_freq = clk_freq
+        self.fpga = fpga
 
     def elaborate(self, platform):
         m = Module()
@@ -480,6 +481,10 @@ class DDR3SoC(SoC, Elaboratable):
             m.submodules.hyperram = hyperram = self.hyperram
             # grrr, same problem with hyperram: not WB4-pipe compliant
             comb += hyperram.bus.stall.eq(hyperram.bus.cyc & ~hyperram.bus.ack)
+            # set 3 top CSn lines to zero for now
+            if self.fpga == 'arty_a7':
+                comb += hyperram.phy.cs[1:].eq(Const(0, 3))
+                comb += hyperram.phy.rst_n.eq(1)
 
         # add blinky lights so we know FPGA is alive
         if platform is not None:
@@ -641,10 +646,10 @@ def build_platform(fpga, firmware):
     if platform is None:
         hyperram_pins = HyperRAMPads()
     elif fpga in ['isim']:
-        hyperram_ios = HyperRAMResource(0, cs_n="B11 B18 G13 D13",
+        hyperram_ios = HyperRAMResource(0, cs_n="V12 V14 V12 U12",
                                         dq="D4 D3 F4 F3 G2 H2 D2 E2",
                                         rwds="U13", rst_n="T13", ck_p="V10",
-                                        # ck_n="D12" - for later (DDR)
+                                        # ck_n="V11" - for later (DDR)
                                         attrs=Attrs(IOSTANDARD="LVCMOS33"))
         platform.add_resources(hyperram_ios)
         hyperram_pins = platform.request("hyperram")