code reordering

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index 4f0e0e9c17d1e5f45d529074294065c73a79e0aa..e4df22274d26fad1243285f453463d9d74fc9b36 100644 (file)
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -110,9 +110,21 @@ class FPCVTMuxInOutBase(ReservationStations):
         return FPPackData(self.out_pspec)
 
 
-def getkls(*args, **kwargs):
-    print ("getkls", args, kwargs)
-    return FPCVTMuxInOutBase(*args, **kwargs)
+class FPCVTF2IntMuxInOut(FPCVTMuxInOutBase):
+    """ Reservation-Station version of FPCVT pipeline.
+
+        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
+        * 2-stage multiplier pipeline
+        * fan-out on outputs (an array of FPPackData: z,mid)
+
+        Fan-in and Fan-out are combinatorial.
+    """
+
+    def __init__(self, in_width, out_width, num_rows, op_wid=0):
+        FPCVTMuxInOutBase.__init__(self, FPCVTFloatToIntMod, False,
+                                         in_width, out_width,
+                                         num_rows, op_wid,
+                                         pkls=FPCVTFtoIntBasePipe)
 
 
 # factory which creates near-identical class structures that differ by
@@ -125,24 +137,12 @@ muxfactoryinput = [("FPCVTDownMuxInOut", FPCVTDownConvertMod, True, ),
                    ("FPCVTIntMuxInOut",   FPCVTIntToFloatMod,   True, ),
                   ]
 
+def getkls(*args, **kwargs):
+    print ("getkls", args, kwargs)
+    return FPCVTMuxInOutBase(*args, **kwargs)
+
 for (name, kls, e_extra) in muxfactoryinput:
     fn = functools.partial(getkls, kls, e_extra)
     setattr(sys.modules[__name__], name, fn)
 
 
-class FPCVTF2IntMuxInOut(FPCVTMuxInOutBase):
-    """ Reservation-Station version of FPCVT pipeline.
-
-        * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
-        * 2-stage multiplier pipeline
-        * fan-out on outputs (an array of FPPackData: z,mid)
-
-        Fan-in and Fan-out are combinatorial.
-    """
-
-    def __init__(self, in_width, out_width, num_rows, op_wid=0):
-        FPCVTMuxInOutBase.__init__(self, FPCVTFloatToIntMod, False,
-                                         in_width, out_width,
-                                         num_rows, op_wid,
-                                         pkls=FPCVTFtoIntBasePipe)
-